Provided is a gate driving circuit comprising: a plurality of gate driving units 1, comprising: a pull-up control unit 200, which is connected to a first and a second nodes Q and N, a first clock signal CK1, a scan signal output terminal G(n), a current stage transmission signal output terminal Cout(n) and a previous stage transmission signal output terminal Cout(n-1); a pull-down maintenance unit 500, which is connected to the first and second nodes Q and N, a current stage feedback signal output terminal Out(n), a next stage feedback signal output terminal Out(n+1), the scan signal output terminal G(n), the current stage transmission signal output terminal Cout(n), a first DC high voltage VGH1, a first and second DC low voltages VGL1 and VGL2; a pull-up unit 100, which is connected to the first node Q, the second clock signal and the scan signal output terminal; a downstream unit 400, which is connected to the first node Q, the second clock signal CK2, a second DC high voltage VGH2, the current stage feedback signal output terminal Out(n), and the current stage transmission signal output terminal Cout(n); a pull-down unit 300, which is connected to the first and second nodes Q and N, the scan signal output terminal G(n), the next stage transmission signal output terminal Out(n+1), and the first and second DC low voltages VGL1 and VGL2; a bootstrap capacitor Cbt, one end of the bootstrap capacitor Cbt is connected to the first node Q, and the other end is connected to the scan signal output terminal G(n).