272results about "Single resonant circuit with varying inductance/capacitance only" patented technology

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an FW+ terminal and the second terminal comprises an RF terminal. In accordance with some embodiments, the DTCs comprises a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second FW terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

A method and apparatus for dynamically varying the impedance of a tank circuit whereby, over time, the response of the circuit to a received signal is maximized.

An integrated variable voltage diode capacitor topology applied to a circuit providing a variable voltage load for controlling variable capacitance. The topology includes a first pair of anti-series varactor diodes, wherein the diode power-law exponent n for the first pair of anti-series varactor diodes in the circuit is equal or greater than 0.5, and the first pair of anti-series varactor diodes have an unequal size ratio that is set to control third-order distortion. The topology also includes a center tap between the first pair anti-series varactor diodes for application of the variable voltage load. In preferred embodiments, a second pair of anti-series varactor diodes is arranged anti-parallel to the first pair of anti-series varactor diodes so the combination of the first pair of anti-series varactor diodes and the second pair of anti-series varactor diodes control second-order distortion as well.

An integrated center frequency selectable resonant coupling network suited for use in an integrated circuit is disclosed. The network includes an integrated coupling transformer having a secondary winding for coupling to a load and a primary winding for coupling to a source; a first integrated capacitive circuit controllably coupled across one of the primary and secondary windings and when so coupled operable to resonate with the integrated coupling transformer at a frequency in a first frequency band; and a second integrated capacitive circuit coupled across a second one of the primary and the secondary windings that is operable to resonate with the integrated coupling transformer at a frequency in a second frequency band. The method is in an IC and includes providing and coupling an input signal within alternatively a first frequency band and a second frequency band to a primary winding of an integrated coupling transformer; controlling an integrated switched capacitor network, coupled to the transformer, to provide a coupling network that is alternatively and respectively resonant at a first and second frequency within the first and second frequency band thus selectively providing an output signal at a secondary winding of the transformer; and down converting the output signal.

An anchor to hold getter materials in place within a micromechanical device package substrate. First and second cavity faces define an anchor cavity and mechanically retain a getter away from a region holding the micromechanical device. The getter anchor may be formed in a substrate comprised of at least three layers. The layers form a cavity in the substrate with a wide bottom portion—formed in the middle layer and a relatively narrower top portion—formed by the top layer. The narrow portion helps to retain the getter in the cavity by creating a mechanical lock on the wide portion of getter in the bottom of the cavity.

A tuner includes a plurality of paths, and at least one of the paths includes a front-end filter circuit, an amplifier, and a trace filter. The trace filter includes a varactor and an inductor, which are coupled to an output end of the amplifier. Further, the amplifier and the varactor of the tuner are packed in a complementary metal-oxide semiconductor (CMOS) chip.

A linear voltage controlled capacitance circuit is provided that includes a plurality of MOS varactor pairs. Each MOS varactor pair is operable to receive a first tuning voltage, a second tuning voltage, and a bias voltage unique to the MOS varactor pair. The capacitance circuit is operable to generate a positive tank node signal and a negative tank node signal based on the first and second tuning voltages and the bias voltages. A means to control voltage-to-capacitance gain is also provided to compensate for coarse tuning capacitance change.

A tuning apparatus is provided, wherein the on and off resistances of semiconductor switches within an tuning IC are optimized, so as to provide high sensitivity and superior stability, a wide range of tuned frequency variation, compactness and high performance. The tuning apparatus has a tuning circuit, which has N-channel MOS transistors (N transistors) 5a through 5f, serving as a plurality of semiconductor switches, and a counter circuit 6, which controls the opening and closing of the N transistors, a plurality of capacitors 4a through 4f, which are each connected in series with the plurality of N transistors, and a receiving antenna 2 wherein the total electrostatic capacitance of the plurality of capacitors is varied by the opening and closing of the plurality of N transistors, thereby varying the frequency tuned by the plurality of capacitors and the receiving antenna.

A passive transponder includes an antenna, an antenna oscillator circuit and a data source. The antenna oscillator circuit is configured to operate at a first resonant frequency or at a second resonant frequency, depending on reception of energy at the transponder or on a data transmission from/to the data source.

A method and apparatus for manufacturing thin RFID tags adapted to be mounted proximate an interfering substance, such as metal or liquid. Each tag comprises: a web substrate having a predetermined thickness; an antenna attached to the substrate; and an RFID integrated circuit connected to the antenna, the RFID integrated circuit comprising a tank circuit adapted to be tuned in response to an RF signal after the tag has been mounted proximate the interfering substance. In one embodiment, the tag is manufactured using roll-to-roll manufacturing technology.

A broadband tuner includes a tracking filter with calibration to compensate for component errors and drift. The filters use off-die inductors that are preferably within a system-in-package (SIP) with other critical tuner components, which produces a highly integrated tuner front end with high Q filters within a single package. High voltage varactors with a large tuning range can be used for variable capacitors. The integration of the tuner into a SIP allows the tuner design to be optimized for cost and performance while keeping the critical RF layout requirements within the tuner. A configurable tuner front end enables modes for low noise, high linearity, good input return loss (S11) across the entire RF band, and applying a test tone in the calibration mode. The switchable mode enables the tuner to be effective during weak terrestrial reception, strong terrestrial reception, and connection to a cable plant.

A tunable capacitance unit coupled between a pair of circuit nodes. The tunable capacitance unit comprises a tuning input supplying a tuning voltage, and first and second tuning capacitance units. Each of the tuning capacitance units comprises a pair of accumulation-mode MOS varactors with source/drains thereof coupled to the tuning input, a pair of blocking capacitors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective one of the circuit nodes, and a pair of biasing resistors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective bias terminal receiving a respective reference voltage. The reference voltages received by the first and second tuning capacitance units are symmetrical to a predetermined voltage.

A frequency multiplier and amplification circuit are disclosed. One embodiment of the present invention comprises: a multiplier operably coupled to multiply a first sinusoidal waveform having a first frequency with a second sinusoidal waveform having a second frequency to produce a third sinusoidal waveform, having a frequency representative of a difference between the first frequency and the second frequency, and a fourth sinusoidal waveform having a frequency representative of a sum of the first and second frequencies; and a frequency-tuned load operably coupled to substantially attenuate the third sinusoidal waveform and to substantially pass the fourth sinusoidal waveform as an output of the frequency-tuned multiplier circuit. The frequency-tuned multiplier circuit can be a single-ended multiplier circuit or a differential multiplier circuit with corresponding single-ended or differential first and second sinusoidal waveforms.