3820results about "Conductive pattern layout details" patented technology

Abstract of the Disclosure Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of one-Gigabyte, two-Gigabyte, and four-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in the first row on a first lateral portion of the printed circuit board and in the second row on the first lateral portion are connected to a first addressing register with two register integrated circuits. The integrated circuits in the first row on the second lateral portion and in the second row on the second lateral portion are connected to a second addressing register with two register integrated circuits. Each addressing register processes a non-contiguous subset of the bits in each data word.

The present invention provides systems and methods for embedding a filament or filament mesh in a three-dimensional structure, structural component, or structural electronic, electromagnetic or electromechanical component / device by providing at least a first layer of a substrate material, and embedding at least a portion of a filament or filament mesh within the first layer of the substrate material such the portion of the filament or filament mesh is substantially flush with a top surface of the first layer and a substrate material in a flowable state is displaced by the portion of the filament and does not substantially protrude above the top surface of the first layer, allowing the continuation of an additive manufacturing process above the embedded filament or filament mesh. A method is provided for creating interlayer mechanical or electrical attachments or connections using filaments within a three-dimensional structure, structural component, or structural electronic, electromagnetic or electromechanical component / device.

The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

An integrated antenna type circuit apparatus which provides excellent circuit characteristics while suppressing an increase in packaging area. The integrated antenna type circuit apparatus includes an insulating base, a semiconductor circuit device, chip parts, a molding resin, an antenna conductor, a ground conductor, and external lead electrodes. The plurality of chip parts are mounted on the insulating base, and are soldered to electrodes of wiring conductors on the top of the insulating base for electric and physical connection. The insulating base has a multilayer structure, being formed by laminating a plurality of insulator layers. The antenna conductor is formed on the bottom of the insulating base. A wiring conductor adjacent to the antenna conductor is provided with the ground conductor so that it overlaps with the antenna conductor.

A capacitive position sensor has a two-layer electrode structure. Drive electrodes extending in a first direction on a first plane on one side of a substrate. Sense electrodes extend in a second direction on a second plane on the other side of the substrate so that the sense electrodes cross the drive electrodes at a plurality of intersections which collectively form a position sensing array. The sense electrodes are provided with branches extending in the first direction part of the way towards each adjacent sense electrode so that end portions of the branches of adjacent sense electrodes co-extend with each other in the first direction separated by a distance sufficiently small that capacitive coupling to the drive electrode adjacent to the co-extending portion is reduced. Providing sense electrode branches allow a sensor to be made which has a greater extent in the first direction for a given number of sense channels, since the co-extending portions provide an interpolating effect. The number of sense electrode branches per drive electrode can be increased which allows a sensor to be made which has ever greater extent in the first direction without having to increase the number of sense channels.

A capacitive touch sensor wherein the touch sensitive panel has drive electrodes arranged on the lower side of a substrate and sense electrodes arranged on the upper side. The drive electrodes are shaped and dimensioned to substantially entirely cover the touch sensitive area with individual drive electrodes being separated from each other by small gaps, the gaps being so small as to be practically invisible. The near blanket coverage by the drive electrodes also serves to screen out interference from noise sources below the drive electrode layer, such as drive signals for an underlying display, thereby suppressing noise pick-up by the sense electrodes that are positioned above the drive electrodes.

A method of patterning a conductor on a substrate includes providing an inked elastomeric stamp inked with self-assembled monolayer-forming molecules and having a relief pattern with raised features. Then the raised features of the inked stamp contact a metal-coated visible light transparent substrate. Then the metal is etched to form an electrically conductive micropattern corresponding to the raised features of the inked stamp on the visible light transparent substrate.

A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

There is presented a high frequency module, in which a recess 2a for mounting power amplifier device is formed on a lower surface of a dielectric substrate 2, and a recess 2b for mounting surface acoustic wave filter is formed on an upper surface of the dielectric substrate 2, and a power amplifier device 4 and a surface acoustic wave filter 8 are mounted through conductive bumps 3a and 3b on the recesses 2a and 2b, respectively. In addition, a through-hole conductor 11 whose one end is exposed at the lower surface of the dielectric substrate 2 is provided between the recesses 2a and 2b. The exposed end of the through-hole conductor 11 is attached to a thermal dissipation conductor 15 on an upper surface of an external electric circuit board 7 through a brazing material 13.

There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and / or utilize the side surface of an assembled flexible display.

An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

There is presented a high frequency module, in which a recess 2a for mounting power amplifier device is formed on a lower surface of a dielectric substrate 2, and a recess 2b for mounting surface acoustic wave filter is formed on an upper surface of the dielectric substrate 2, and a power amplifier device 4 and a surface acoustic wave filter 8 are mounted through conductive bumps 3a and 3b on the recesses 2a and 2b, respectively. In addition, a through-hole conductor 11 whose one end is exposed at the lower surface of the dielectric substrate 2 is provided between the recesses 2a and 2b. The exposed end of the through-hole conductor 11 is attached to a thermal dissipation conductor 15 on an upper surface of an external electric circuit board 7 through a brazing material 13.

A high-frequency module has a structure wherein transmitting filters, receiving filters and high-frequency power amplifiers are mounted on a multilayered substrate and wherein matching circuits are inserted between input terminals of the receiving filters and output terminals of the transmitting filters. Transmission lines as components of the matching circuits, and the like are formed internally of the multilayered substrate. Thus, the whole body of the high-frequency module can be downsized.

A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.

Each unit pixel of an active-matrix-driven organic EL display device includes a pixel EL element and an associated pixel circuit. An array of the pixel EL elements are formed on the front surface of a multilayer substrate, the rear surface of which mounts thereon a drive IC and the plurality of pixel circuits. The electrodes of the drive IC are connected to the anode and cathodes of the pixel EL elements through via holes and interconnects formed in the multilayer substrate.< / PTEXT>

A insulation displacement connector (IDC) patch panel includes a circuit (PC) board with interdigitated capacitance for balancing out inherent capacitance found within IDCs of the panel and conventional plug connectors coupled to the panel. Unwanted cross-talk signals are reduced as a consequence.

A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid FR-4 laminate, a polyimide, a polymer or a multilayer PCB via a process such as screen or stencil printing. In one embodiment, the VVM includes two types of conductive particles, one with a core and one without a core. The VVM can also have core-shell type semiconductive particles.

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

It will be understood by those skilled in the art that there is disclosed in the present application a biometric sensor that may comprise a plurality of a first type of signal traces formed on a first surface of a first layer of a multi-layer laminate package; at least one trace of a second type, formed on a second surface of the first layer or on a first surface of a second layer of the multi-layer laminate package; and connection vias in at least the first layer electrically connecting the signal traces of the first type or the signal traces of the second type to respective circuitry of the respective first or second type contained in an integrated circuit physically and electrically connected to one of the first layer, the second layer or a third layer of the multilayer laminate package.

A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes a first compensation structure provided on an inner metalized layer of the PCB at a first stage area of the PCB, and a second compensation structure, provided at a second stage area of the PCB, for increasing compensation capacitance with increasing frequency.

A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a substrate (first substrate) (101) that has a luminous element (102) formed thereon. A PWB side wiring (second group of wirings) (110) on the printed wiring board (107) is electrically connected to element side wirings (first group of wirings) (103, 104) by anisotropic conductive films (105a, 105b). At this point, because a low resistant copper foil is used to form the PWB side wiring (110), a voltage drop of the element side wirings (103, 104) and a delay of a signal can be reduced. Accordingly, the homogeneity of the quality of an image is improved, and the operating speed of a driver circuit portion is enhanced.

A touch panel structure and the manufacturing method thereof are disclosed, in which the manufacturing method includes the steps of: providing a bonding layer; and forming a conductive pattern layer on the bonding layer; wherein the conductive pattern layer is composed of at least one first and at least one second major conductors with an insulation layer interposed between the first and the second major conductors. Comparing with the prior art for manufacturing touch panels, the disclosure is advantageous in material cost, production cost, and production yield; moreover, the panel lamination process can be simplified and the touch panel structure can be joined to a planar or curvy panel and facilitate the design of a thinner product.

Electrical mounting boards and methods for their fabrication and use are disclosed herein. In particular, such mounting boards embodiments utilize hybrid ground lines interconnected through a substrate core to form multilayer ground grids. Such hybrid ground lines include groups of substantially parallel ground lines configured such that the groups of ground lines are positioned in transverse arrangement with other groups of ground lines formed on the same level. Such implementations have many uses, including, but not limited to, the ability to more efficiently route signal lines and connect electrical components on a circuit board.

Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, or selective metallization of the array followed by filling the array with a filler material and a second selective metallization on the filled microcavity array. The thus prepared filled conductive microcavity array is then over-coated or laminated with an adhesive film. Cavities in the array, and particles filling the cavities, can have a unimodal, bimodal, or multimodal distribution.

The idea of the invention is to fabricate a multilayer coaxial transmission line into a printed circuit. The outermost conductor is fabricated by conductive conduit strips in different layers, using conductive via posts in isolation layers connecting the strips. The innermost conductor can be a single conductive strip or multiple strips in different layers connected together through conductive via posts.

A substrate having a transparent conductive layer has a transparent conductive pattern that is not easily visually recognizable by a naked human eye on a transparent substrate and can be formed by a simple and efficient method. In the case where a transparent conductive pattern is formed on a transparent substrate, the pattern region does not include conductive regions covered with uniform transparent conductive films or a high-resistance region that is not covered with the transparent conductive film, the high-resistance region electrically insulating the conductive regions. Instead of the conductive regions or the high-resistance region, the inventors use a region having a structure including a mixture of a portion covered with the transparent conductive film and a portion not covered with the transparent conductive film, thereby solving the foregoing visual recognition issue.

A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid FR-4 laminate, a polyimide, a polymer or a multilayer PCB via a process such as screen or stencil printing. In one embodiment, the VVM includes two types of conductive particles, one with a core and one without a core. The VVM can also have core-shell type semiconductive particles.

Electromagnetic Bandgap (EBG) structures are embedded between adjacent power planes in a multi-layer PCB to decrease the emanation of Electromagnetic radiation induced by power buses, signal layers, as well as to suppress the switching noise. EBG stages with different stop bands are cascaded to create rejection over a wider frequency region. The cascading can be performed in series, or may be formed in a variety of arrangements such as a checkerboard design or concentric ribbons positioned along the perimeter of the PCB. Each EBG stage is composed of conductive patches and via posts extending from each patch, which are positioned at a predetermined distance from each other. By surrounding the source of the noise with EBG stages, a sufficient suppression of electromagnetic noise over specific frequency bands of interest is achieved.