The invention discloses a method and
system for repairing
time sequence violations in
chip design, and relates to the technical field of
integrated circuit design. The method comprises the following steps of selecting a target repair path from
time sequence violation paths, grabbing all basic units and the
delay values corresponding to the basic units in the target repair path and sorting, and sequentially selecting the basic units as the target units according to the sequence; judging whether the violation is an establishment time violation or a
retention time violation, replacing the targetunits sequentially based on the rules which do not affect other
time sequence paths, and obtaining the repair operation meeting requirements; and converting the repair operation into an operation command which can be identified by a
layout wiring tool, executing the operation on the
layout wiring tool, and ending the repair under the condition of verifying that the time
sequence analysis result after the operation meets the time sequence requirement. According to the invention, when the time sequence violation repair is carried out, the re-
layout and the re-wiring are not needed, and the timesequence convergence can be realized through the rapid iteration.