The invention relates to a memory aggregation device (990) for storing a set of input data streams (902) and retrieving data to a set of output data streams (904), both the set of input data streams (902) and the set of output data streams (904) being operable to perform one of sending and stop sending new data in each
clock cycle, the memory aggregation device (990) comprising: a set of FIFO memories (901a, 901b,..., 901c) each comprising an input and an output; an input
interconnector (903) configured to interconnect each one of the set of input data streams (902) to each input of the set of FIFO memories (901a, 901b,..., 901c) according to an input
interconnection matrix; an output
interconnector (905) configured to interconnect each output of the set of FIFO memories (901a, 901b,..., 901c) to each one of the set of output data streams (904) according to an output
interconnection matrix; an input selector (907) configured to select the input
interconnection matrix according to an input
data scheduling scheme; an output selector (909) configured to select the output
interconnection matrix according to an output
data scheduling scheme; and a
memory controller (911) coupled to both, the input selector (907) and the output selector (909), wherein the
memory controller (911) is configured to control the input
data scheduling scheme such that data from the set of input data streams (902) is spread among the set of FIFO memories (901a, 901b,..., 901c) in a round-robin manner and to control the output data scheduling scheme such that data from the set of FIFO memories (901a, 901b,..., 901c) is retrieved to the set of output data streams (904) in a round-robin manner.