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249 results about "Image reduction" patented technology

Detecting and error-correcting method capable of rapidly and accurately obtaining element center and deflection angle

A detecting and error-correcting method capable of rapidly and accurately obtaining an element center and a deflection angle is disclosed. Interested edge area can be rapidly and accurately found out through an automatic edge area extraction method based on combination of binary morphology and image reduction, and subsequent edge extraction image scope is minimized as possible. Pixel level edge is roughly positioned at first, and accordingly a sub-pixel edge is rapidly extracted by one-dimensional curve fitting method. The method overcomes the defect of complex algorithm of a conventional sub-pixel edge extraction algorithm based on two-dimensional images, and the time of extracting accurate sub-pixel edge can be shortened. Weighted least square rectangular edge fitting algorithm based on linear hazen paradigm can detect straight lines on any positions of an image, and effectively minimizes influence of outlier on fitting precision due to uneven edges. The central positions of a plurality of elements and deflect angles can be rapidly and accurately detected at once, and the efficiency of visual detection is improved.
Owner:GUANGDONG UNIV OF TECH

Video signal processing circuit inhibiting display of distorted images

A video signal processing circuit uses a buffer memory for reducing or expanding video signals in the generation of child images to be displayed within a display window. Image size data, stored in a header within the buffer memory, and a reduced video signal are prevented from representing different image reduction ratios which might otherwise occur when the reduction ratio is changed. At the time of changing the reduction ratio, image size data SIZ are calculated from a write enable signal based on reduction ratio data K, for a one-field period just after the change by an input video clock generator 22. The calculated image size data are written to a header together with a reduced video signal in a field memory 2, and a flag bit SP indicating the change in the reduction ratio is also written to the header for the one-field period just after the change. When data are read from the buffer memory, the flag bit SP is detected by a display video clock generator 23 to mute a video signal output when there is a likelihood of displaying distorted data. On the other hand, writing to the field memory 2 is inhibited for the one-field period just after the change in the image magnification data so that the muting period of the video signal output can be shortened.
Owner:SEMICON COMPONENTS IND LLC
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