84 results about "AN codes" patented technology

A code ID range table holding code ID ranges for each code and a next code ID table holding next code IDs, which are the code ID located next to each code ID, are created. Code ID ranges of codes configuring a search code string are read out from the code ID range table for the search target code string, and the stored next code ID corresponding to a code ID included in the code ID range of the head code in the search code string is read out from the next code ID table while the stored next code IDs corresponding to the next codes are successively read out from the next code ID table, and the next code ID read out from the next code ID table is verified whether it is included in the code ID range read out from the code ID range table.

A comparison graph is disclosed. A system for comparing code branches comprises a code branch separator for determining a first set of commits in a first code branch that are not common to a second code branch, and determining a second set of commits in the second code branch that are not common to the first code branch; and a user interface determiner for determining a display of the first set of commits and the second set of commits.

Multiple-access codes are generated using an asymptotically optimal decoding algorithm, such as the Viterbi algorithm. A trellis may be constructed using a number of desired users, at least one code length, and a number of code-chip parameters. A fitness function is derived from a mathematical relationship between the multiple-access codes, and may include some measure of correlation of the codes. The multiple-access codes correspond to paths having optimal path metrics derived from the fitness function. Multiple iterations through the trellis may be performed to refine a selection of multiple-access codes.

The invention relates to a method and apparatus for generating simple patterns on a terminal and conveying them in a communications network. In the method, an element of a pattern (201, 301) comprising elements is specified and it is assigned a code by which it is identified. The codes of the elements in a pattern are used in compiling a set of codes (303a, 303b, 303c) which describes identified elements of the pattern. The set of codes (303a, 303b, 303c) is sent into a communications network in addition to the message. The receiving device receives, in addition to the message, the set of codes (303a, 303b, 303c) containing the codes of the elements in the pattern (201, 301), which set of codes is analyzed (406) and identified. Element codes included in the set of codes (303a, 303b, 303c) are used to identify elements used to generate a pattern (201, 301).

The need for separate CRC bits is eliminated by taking advantage of what has been determined to be an embedded error detection capability in a turbo code itself to perform error detection following turbo decoding. Specifically, since the two constituent encoders of a turbo encoder that are used to encode a data packet produce two systematic codes that share the same systematic bits one code, one is used to serve as the parity check for the other. The sign of the log likelihood ratio (LLR) of each systematic bit in a block of decoded data calculated at the end of a turbo decoding cycle is compared with the sign of the LLR of each corresponding bit that was calculated at a previous turbo decoding cycle. If the signs of the LLRs for each comparison do not agree, then a packet error is determined to have occurred; otherwise no packet error is detected.

A method of generating a code sequence comprises populating at least one buffer with initial values based on a received spreading factor and desired code index; receiving a timing strobe; changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and outputting at least one code sequence value based on the values in the at least one buffer. An apparatus for generating a code sequence comprises means for populating at least one buffer with initial values based on a received spreading factor and desired code index; means for receiving a timing strobe; means for changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and means for outputting at least one code sequence value based on the values in the at least one buffer.

A method of generating a code sequence comprises populating at least one buffer with initial values based on a received spreading factor and desired code index; receiving a timing strobe; changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and outputting at least one code sequence value based on the values in the at least one buffer. An apparatus for generating a code sequence comprises means for populating at least one buffer with initial values based on a received spreading factor and desired code index; means for receiving a timing strobe; means for changing the values in the at least one buffer upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe; and means for outputting at least one code sequence value based on the values in the at least one buffer.

A lock and key combination is disclosed, offering a large number of codes. The combination includes a lock (200) of the kind comprising a housing having a cylindrical bore, a cylindrical key plug (202) and a number of locking pins (205a-205g) in a row along a key plug axis for locking the key plug against rotation in the cylindrical bore, and a key (100) of the kind comprising a longitudinally extending, substantially flat key blade (102), with at least two longitudinally extending formations. The key blade comprises an upper edge portion having a first code pattern (103) and a lower, massive portion having a second code pattern (104). At least one of the locking pins in said row is a short pin (205a, 205b, 205c) comprising a first, relatively short key sensing part (207, 208) cooperating with the first code pattern (103), and at least another one of the locking pins in said row is a long pin (205f, 205g, 205h) comprising a second, relatively long key sensing part (210, 207, 208) cooperating with the second code pattern (104).

The invention provides a code processing method and device, a server and a storage medium, and belongs to the technical field of computers. The method comprises: based on at least one code branch of any code processing item and a first code processing operation executed on the code branch, determining a first workflow type from at least one standard workflow type, and the first workflow type corresponding to at least one operation specification; for any code branch of the code processing project, obtaining any second code processing operation performed on the code branch, determining a first target operation specification corresponding to the second code processing operation from the at least one operation specification, and comparing the second code processing operation with the first target operation specification; and if the second code processing operation is not matched with the first target operation specification, outputting a monitoring result. In the application, the server can assist the development team to apply the standard workflow more accurately and efficiently, so that the collaborative development efficiency of the development team is higher.

Multiple-access codes are generated using an asymptotically optimal decoding algorithm, such as the Viterbi algorithm. A trellis may be constructed using a number of desired users, at least one code length, and a number of code-chip parameters. A fitness function is derived from a mathematical relationship between the multiple-access codes, and may include some measure of correlation of the codes. The multiple-access codes correspond to paths having optimal path metrics derived from the fitness function. Multiple iterations through the trellis may be performed to refine a selection of multiple-access codes.

Method of identification and compensation for inversion of the input bit stream when decoding LDPC codes includes obtaining a code word of the LDPC code from a demodulator output and writing the code word into a buffer memory, decoding the code word, calculating a syndrome for each iteration when decoding, making an analysis of converging the weight of the syndrome, generating an inversion feature for the input bit stream based on this analysis, continuing the decoding, if the inversion feature for the input bit stream does not give evidence of detecting inversion, resetting, if the inversion feature for the input bit stream shows inversion, the LDPC decoder and analysis parameters for the convergence of the weight of the syndrome, reading next code word from the buffer memory, and producing an inversion of this code word, and feeding the word to the decoder input to implement the next decoding operation.

The present invention is directed toward a parity check encoder for low density error correction codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes.

An extended deinterleaver the extended deinterleaver being responsive to at least one input signal, comprised of codewords, and operative to generate a deinterleaved output signal. The extended deinterleaver comprising a storage space organized into B number of appended storage branches, at least one appended storage branch having a storage branch and at least one element N, the received codewords being deinterleaved and buffered by the extended deinterleaver prior to being provided to the variable iteration decoder. Each appended storage branch further having a length that is extended by the length of N, N being at least one element, wherein as a codeword is provided to the variable iteration decoder, other codewords are provided to subsequent appended storage branches, and further wherein each appended storage branch, indexed by ‘b’, has a length of Lb+N, wherein Lb is the length of the storage branch prior to appending N.

Subversive DSV (SDSV) sequences of data symbols having a large absolute value of DSV are extremely valuable in the copy protection of optical discs as they can induce uncorrectable read errors. However, very few SDSV sequences of data symbols can be found in multimodal codes such as Eight-to-Sixteen Modulation (ESM) utilised in DVDs. It is required to select data symbols, for encoding using a multimodal code, which are capable of forcing an encoder to produce at least one subversive sequence of code words. A possible code word for a data symbol is selected if the code word has a large absolute value of DSV and there are no alternative code words, or all alternative code words are equivalent, or all alternatives except one are ruled out by RLL rules.