266results about How to "Shorten programming time" patented technology

The present invention relates to erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method according to the present invention, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

A method and a system for use in connection with programming of an industrial robot, the programming comprises teaching the robot a path having a number of waypoints located on or in the vicinity of an object to be processed by the robot. The system comprises: means for obtaining information about the waypoints of the path in relation to the object, a storage unit (16), for storing the obtained information, a simulation unit (18), simulating the robot path based on the obtained information about the waypoints and a model of the robot, a graphics generator (23), generating a graphical representation of the simulated robot path, and a display member (12) displaying a view comprising the object and said graphical representation of the robot path projected on the object.

Method and device for programming control information, such as a flag, a control flag, a mark, or a control mark. The method and device may perform a lower-speed programming of a given cell type in a first area of memory array, confirm a result of the lower-speed programming of the given cell type in the first area of memory array, and perform a higher-speed programming of the given cell type in a second area of memory array after confirming the result of the lower-speed programming, wherein an initial programming voltage of the higher-speed programming may be different from that of the lower-speed programming. The first and second programming may be different, for example, the first programming may be a lower-speed operation, such as the writing of data, and the second programming may be a higher-speed operation, such as the writing of control information. The first and second programming methods may also be different, for example, the first programming method may be a programming method that does not permit over-programming and the second programming method may be a programming method that does permit over-programming.

The present invention provides a Docker container management method and system. The method comprises: receiving a trigger instruction of a create button for creating at least one Docker container on a visual interface; according to a preset scheduling policy, assigning a physical machine capable of creating the Docker container and an IP address of the Docker container from physical machines and IP addresses to be scheduled; according a preconfigured script parameter rule on execution of Docker container creation, and the assigned physical machine and IP address, generating a command of executing the creation of the Docker container; and executing the command to create the Docker container on the physical machine. According to the present invention, the utilization of a visual interface to create a Docker container is more intuitive, simpler, and higher in operability, and also can provide an automated creation process with no need of manual involvement and with high efficiency.

The invention discloses a method for implementing code programming by graphical operations. The method is involved with a node module, a testing environment module, a flow chart module, a function module and a code output module. The node module is used for establishing test nodes corresponding to test programs according to different devices to be tested, related test devices and the corresponding test programs. The testing environment module is used for establishing a current operating environment for the flow chart module according to information of the device to tested, selected by a user. The flow chart module is used by the user to sequentially establish graphic flow charts formed by the test nodes according to the devices predicted for testing and the test nodes selected in correspondence to the corresponding test devices. The function module is used for storing and recording new functions and for supporting function calls regarding to the node module and the flow chart module. The code output module is used for converting the generated graphic flow charts into executable files formed by codes and outputting the files. The method is compatible with various testing environments (operating systems and CPU (central processing unit) environments) and is capable of providing graphical interface editing and testing logics to users and visually displaying the operating process and testing implication of function modules.

The invention relates to an industrial robot comprehensive control platform and a control method thereof. The industrial robot comprehensive control platform comprises an object modeling module, a parameter setting module, a database module, a spray gun path generation module, a robot motion path generation module, a man-machine interaction module, an analysis and display module, an operation command generation module and a communication and interface module. The invention has the advantages that the functions are complete, the commonality is high, the robot program development cycle is shortened, the painting accuracy of the system is improved, the production cost is reduced, the production efficiency is improved, the requirements on the technical capability of operators are reduced, the economic benefit is high and the platform can be easily accepted by users.

A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.