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33results about How to "Reliability issue" patented technology

SRAM cell with column select line

ActiveUS7164596B1Optimum static noise marginMinimizing data upsetDigital storageLow voltageHigh pressure
An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.
Owner:TEXAS INSTR INC

Parallel RIP with Preamble Caching

A method and system is provided for splitting a print job into its preamble and at least one chunk. The splitter maintains a collection of RIP node addresses to which chunks of the job currently being split have already been sent. When a new chunk is about to be sent, the splitter checks whether each RIP node address has already received a chunk. If the RIP node has not already received a chunk, the splitter sends the preamble as well as the chunk to an available RIP associated with the RIP node. If, however, the RIP node address has already received a chunk, only the portion of the chunk after the preamble is sent to an available RIP associated with the RIP node and communicate the location of the preamble to the available RIP node. The preamble may contain common content for each job.
Owner:XEROX CORP

Charge pump circuit suitable for low-voltage process

The present invention discloses a charge pump circuit suitable for a low-voltage process. The charge pump circuit is composed of stages of the voltage amplifying circuits connected each other, and the operation of two adjacent stages of voltage amplifying circuit is controlled by two opposite set of the timing signals. Each stage of the voltage amplifying circuit has a coupled pair of a first complementary MOS (CMOS) transistor and a second CMOS transistor switching in accordance with a timing signal and an inverse timing signal inputted into the first and second capacitors. Then, two diode devices guide charges to next stage, and a voltage higher than the integrated circuit voltage source is outputted. The present invention has advantage of high pumping gain, and the reliability issue of the gate oxide layer in the low-voltage process can be also solved.
Owner:NAT CHIAO TUNG UNIV

High-voltage tolerant power-rail ESD clamp circuit

A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.
Owner:NATIONAL CHIAO TUNG UNIVERSITY

Structure and fabricating method with self-aligned bit line contact to word line in split gate flash

A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.
Owner:TAIWAN SEMICON MFG CO LTD

ESD device layout for effectively reducing internal circuit area and avoiding ESD and breakdown damage and effectively protecting high voltage IC

An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I / O device have a better ESD protection capability. Accordingly, by properly adjusting the breakdown voltage of ESD device within I / O circuit, i.e. adjusting the distance between the edge of n-well and the battlement layout pattern of heavily doped regions, it will help to reduce the chip area and improve the ESD reliability.
Owner:HIMAX TECH LTD
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