34results about How to "Reliability issue" patented technology

The present invention discloses a charge pump circuit suitable for a low-voltage process. The charge pump circuit is composed of stages of the voltage amplifying circuits connected each other, and the operation of two adjacent stages of voltage amplifying circuit is controlled by two opposite set of the timing signals. Each stage of the voltage amplifying circuit has a coupled pair of a first complementary MOS (CMOS) transistor and a second CMOS transistor switching in accordance with a timing signal and an inverse timing signal inputted into the first and second capacitors. Then, two diode devices guide charges to next stage, and a voltage higher than the integrated circuit voltage source is outputted. The present invention has advantage of high pumping gain, and the reliability issue of the gate oxide layer in the low-voltage process can be also solved.

An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.

A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad.

A method and system is provided for splitting a print job into its preamble and at least one chunk. The splitter maintains a collection of RIP node addresses to which chunks of the job currently being split have already been sent. When a new chunk is about to be sent, the splitter checks whether each RIP node address has already received a chunk. If the RIP node has not already received a chunk, the splitter sends the preamble as well as the chunk to an available RIP associated with the RIP node. If, however, the RIP node address has already received a chunk, only the portion of the chunk after the preamble is sent to an available RIP associated with the RIP node and communicate the location of the preamble to the available RIP node. The preamble may contain common content for each job.

A method of making a glass article, for example a glass light guide plate comprising at least one structured surface including a plurality of channels and peaks. The glass article may be suitable for enabling one dimensional dimming when used in a backlight unit for use as an illuminator for liquid crystal display devices.

A semiconductor device includes first and second nitride semiconductor layers, a source, a drain, a gate structure, first and second p-type doped nitride semiconductor compound islands. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The source, the drain, and the gate structure are disposed on the second nitride semiconductor layer. The drain viewed in a direction normal to the second nitride semiconductor layer extends longitudinally in an extending direction. The gate structure is between the source and the drain. The first p-type doped nitride semiconductor compound islands are disposed on the second nitride semiconductor layer and arranged adjacent to the drain along the extending direction. The second p-type doped nitride semiconductor compound island is disposed between the gate structure and the second nitride semiconductor layer.

This invention relates to a data communication system / method for use in a downhole application wherein electrical energy is supplied over a multiple-conductor power cable to a motor assembly of a downhole tool such as an electric submersible pump. A power leg coupling interfaces a surface controller of a downhole instrument to the conductors of the tool's power cable. Uplink communication of telemetry data occurs via current modulation generated by the downhole instrument and interpreted by a surface controller. Downlink communication of downhole instrument data occurs over a different communication scheme supported by the downhole and surface controllers. Downlink communication scheme provides a supply of power to the downhole instrument. Protection of downhole electronics and continuity of communication is ensured in the event of a ground fault on the power cable. Both downlink and uplink communication frequencies are adaptive based on frequencies and voltages present on the power cable.

An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I / O device have a better ESD protection capability. Accordingly, by properly adjusting the breakdown voltage of ESD device within I / O circuit, i.e. adjusting the distance between the edge of n-well and the battlement layout pattern of heavily doped regions, it will help to reduce the chip area and improve the ESD reliability.

An OLED device according to an example embodiment includes an organic light-emitting element between a lower substrate and an upper substrate. At least a part of a side surface of the upper substrate has a reverse-tapered shape configured to reduce damage to the lower substrate caused by deformation of the upper substrate due to an external impact. Accordingly, reliability issues resulting from a short circuit or burnt lines due to the deformation of the upper substrate may be resolved, improving overall reliability and productivity of an OLED device.