35results about How to "Reduce data dependence" patented technology

A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.

A system for parallel execution of program portions on different processors permits speculative execution of the program portions before a determination is made as to whether there is a data dependency between the portion and older but unexecuted portions. Before commitment of the program portions in a sequential execution order, data dependencies are resolved through a token system that tracks read access and write access to data elements accessed by the program portions.

The invention discloses a median filtering method, device and filter adapted to pipeline architecture, including S101: receiving a numerical sequence; S102: forming a first numerical subsequence according to a filtering window, and finding the numerical median therein; S103: according to Arranging the numerical sequence, sliding the filter window so that after a numerical value is moved in and a numerical value is removed, the first numerical subsequence in the first sequence window becomes the second numerical subsequence; S104: shift the entered numerical value 、 The removed value is compared with the median value in the first numerical subsequence, and a logical operation is performed according to the comparison result to obtain the numerical median value in the second numerical subsequence; S105: sliding filter window, loop through steps S103 to S104 until the numerical sequence The filtering is finished; S106: Save the median value sequentially, and output a sequence of median values. The filtering algorithm in this application has a simple logical structure, avoids maintaining complex data structures, and has low data dependence in the loop body, which is convenient for pipeline and parallelization, so as to achieve the effect of improving fast calculation.

The invention belongs to the technical field of visible light communication, and specifically relates to a machine learning multi-band carrier-free amplitude-phase (multi-band CAP) modulation system based on independent element analysis (ICA). The system of the present invention mainly includes matched filtering & down-sampling, first-level CAP forming and cross-matching filtering, ICA sub-band signal purification, each sub-band signal recovery phase offset, second-level CAP forming and cross-matching filtering, and subtracting sub-band interference , least mean square filter and other modules. In the present invention, after inversion of sub-band interference at the receiving end, it is sent to ICA together with the original received sub-band signal to initially purify each sub-band signal, and then through the second-stage sub-band interference inversion and subtracting the inter-sub-band interference, and then use the second level of equalization to eliminate the guard interval between sub-bands, improve the tolerance of the system to aliasing between sub-bands, achieve the same transmission rate with less bandwidth, and use the signal bandwidth more effectively , to improve the spectrum utilization of the visible light communication system.

The invention discloses a non-supervised change detection method based on two phases of high-resolution remote sensing images. The method includes the following steps: Step 1. The two phases of remote sensing images before the event and after the event in the area to be detected are respectively registered in space, so that Geographic areas at the same location overlap; Step 2: Solve the relative change range image between the two phases of remote sensing images before and after the event; Step 3: Based on the relative change range image, establish the relationship between the minimum value threshold and the maximum value threshold Multi-threshold intervals; step 4, use multi-threshold intervals, and set an increase step S to form multiple binarized change area detection results; step 5, perform fusion processing on multiple binarized change area detection results to obtain optimization Binarized change region detection results of . Using the unsupervised change detection method based on two-stage high-resolution remote sensing images, the threshold setting can be effectively avoided in the process, and the data dependence of the algorithm can be effectively reduced.

The invention provides a quality scalable method for solving the problems of network isomerism and the unreliable network encountered in 3D video coding, and discloses a 3D quality scalable video coding method based on HEVC. According to the scheme, the following two situations are considered; firstly, in order to obtain a higher compression ratio, it is kept that 3D quality scalable video coding is compatible with HEVC, meanwhile, interlayer structure prediction (also known as interlayer reconstruction prediction) is introduced to remove interlayer redundancy, and the interlayer structure prediction processes a video image and a depth image and predicts an enhancement layer by carrying out up-sampling on a reconstruction block of a base layer; secondly, as the depth image has the characteristic of smooth blocks and sharp edges, a special interlayer undistorted prediction method is provided so as to further eliminate interlayer redundancy. The data dependence on the enhancement layer by the interlayer undistorted prediction is reduced through data of an undistorted block of the base layer so that the code rate can be decreased. The interlayer undistorted prediction comprises the two situations including interlayer undistorted intra-frame prediction and interlayer undistorted simple depth coding prediction (namely the interlayer undistorted SDC prediction).

The present invention is related to a digital circuit for use in a mixed-signal circuit. The digital circuit comprises:a first circuit for direct digital synthesis comprising a first phase generator (PG1) arranged for being fed with a phase generator input signal, a first phase-to-amplitude converter (PAC1) arranged for being fed with a phase from the first phase generator and for generating a first carrier wave output, and first signal combining means (R1) for combining the first carrier wave output with a first input signal,a noise generator (NG) arranged for generating a pseudo-random noise signal,combining means (S) for combining the pseudo-random noise signal and the phase generator input signal such that the phase generator input signal to the first phase generator (PG1) is randomised,a second circuit for direct digital synthesis comprising a second phase generator (PG2) arranged for being fed with the pseudo-random noise signal, a second phase-to-amplitude converter (PAC2) arranged for being fed with a phase from the second phase generator and for generating a second carrier wave output, and second signal combining means (R2) for combining the second carrier wave output with a second input signal, whereby the second carrier wave output combined with the second input signal is comprised in the first input signal.