The invention discloses a hardware programmable heterogeneous multi-core system-on-chip, and belongs to the technical field of integrated circuits. According to the system-on-chip, a multi-core DSP, amulti-core MPU, a GPU, an FPGA and a plurality of IP components are organically combined together through an on-chip high-speed bus interconnection network to form a hardware-programmable and processor-multi-core heterogeneous system-on-chip chip, and the specialty of each heterogeneous core is brought into full play. Through an area formed by the multi-core DSP and the FPGA, services such as high-throughput-rate data preprocessing, dense data operation and a bottom-layer algorithm are realized; and an area formed by the multi-core MPU, the GPU and the FPGA accelerator is used for achieving services such as a user interface, a high-level algorithm, application program running and network transmission. The FPGA can also realize a hardware acceleration function required in a multi-core DSPand a multi-core MPU. Based on hardware reconfiguration, the chip architecture improves the flexibility of system-on-chip integration and the expandability and upgradability of later products.