The invention relates to a high-speed parallel acquisition
system clock synchronization device. According to the synchronization device, a
signal conditioning unit is configured; a
clock input amplitude range is set; before a switch unit is switched on,
signal amplitude is increased to be sufficient to make a post-
amplifier saturate; and therefore,
clock signals at a triggering initial time point can be consistently identified at each channel, and the synchronization of a multi-
channel data acquisition
system can be realized. With the synchronization device adopted, the
synchronism of the
data acquisition system is concentrated on the switching on and switching off of a
radio frequency switch, and the transient time of the switching on and switching off of the switch can be substantially compressed, and error influences caused by clock
jitter at an A / D sampling starting position can be eliminated, and therefore,
clock signal amplitude can be consistently identified at each channel, and excellent stability and reliability can be realized; and the extremely-low
phase noise characteristic of a
radio frequency circuit is utilized, so that single ended-to-differential
low noise conversion of high-speed clock signals can be completed, and the utilization efficiency of the device can be improved, and the size of the device can be effectively reduced, and the realization of the
miniaturization of circuits can be benefitted.