295 results about "Receiver front end" patented technology

Pushbroom and flash lidar operations outside the visible spectrum, most preferably in near-IR but also in IR and UV, are enabled by inserting—ahead of a generally conventional lidar receiver front end—a device that receives light scattered from objects and in response forms corresponding light of a different wavelength from the scattered light. Detailed implementations using arrays of discrete COTS components—most preferably PIN diodes and VCSELs, with intervening semicustom amplifiers—are discussed, as is use of a known monolithic converter. Differential and ratioing multispectral measurements, particularly including UV data, are enabled through either spatial-sharing (e. g. plural-slit) or time-sharing.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

An incompressible receiver for minimizing undesired higher-order nonlinear distortion products includes a first receiver path configured to receive an input signal having at least one non-baseband frequency. A second receiver path is also configured to receive the input signal. The second receiver path includes at least one odd-order nonlinear distortion reference component and at least one even-order nonlinear distortion reference component. The distortion reference components are configured to be in an “on” state or in an “off” state. A combining element is configured to combine input signals from the first and second receiver paths such that the higher-order nonlinear distortion signals are substantially attenuated at an output of the combining element. An incompressible receiver that has an odd-order nonlinear distortion reference generator including a cubic term and at least one additional term of order greater than 3 and an incompressible receiver front end amplifier (IRFEA) are also described.

An implantable medical device (“IMD”) as described herein includes adjustable power characteristics such as variable transmitter output power and variable receiver front end gain. These power characteristics are adjusted based upon the intended or actual implant depth of the IMD. The IMD may process an IMD implant depth value (provided by an external IMD programming device) to generate power scaling instructions or control signals that are interpreted by the IMD transmitter and / or the IMD receiver. Such adjustability enables the IMD to satisfy minimum telemetry requirements in a manner that does not waste power, thus extending the IMD battery life.

An apparatus for and method of extending the dynamic range of a RF communications receiver. The invention provides a mechanism for controlling the gain of both the LNA and down conversion mixer in the front end portion of an RF receiver. Both the LNA and the mixer are adapted to have both low and high gain modes of operation. The control mechanism typically comprises a two bit gain control that places both the LNA and mixer in one of four operating gain mode states. The selection of the most appropriate operating gain mode state, is preferably determined in accordance with various metrics such as the received levels of the desired signal, levels of interference signals, bit error rate and receiver RSSI.

An impedance matching system may be used, for example, for impedance matching between a transmitter / receiver front-end and an antenna in a mobile communication device. In a tuneable impedance matching system according to the invention a tuneable impedance matching circuit (508) is used also as a measuring circuit for obtaining a value of a load impedance. A real part and an imaginary part of a load impedance (503) is calculated based on voltages measured on nodes of the tuneable impedance matching circuit and on known component values of the tuneable impedance matching circuit. Values for adjustable electrical components (504, 505) of the tuneable impedance matching circuit are determined based on the obtained load impedance value and on an impedance matching condition.

An integrated multimode radio includes a multimode receiver and a multimode transmitter. The multimode receiver includes a shared receiver front-end, a receiver multiplexor, and a plurality of receiver IF stages. The multimode transmitter includes a shared transmitter front-end, a transmitter multiplexor, and a plurality of transmitter IF stages.

A communication system is presented. The system includes one or more transmitters configured to transmit a signal, where each of the signals generated by the one or more transmitters corresponds to a respective frequency. Further, the system includes a plurality of receiver front-ends configured to receive the signal transmitted by each of the one or more transmitters. The system also includes a plurality of remodulator modules configured to translate each of the received signals to a signal having a respective intermediate frequency. In addition, the system includes a combining module configured to combine each of the signals having respective intermediate frequencies to generate a single composite signal. Also, the system includes a single analog-to-digital converter configured to process the composite signal and generate a digital output. Additionally, the system includes a digital signal processor module configured to extract the signal transmitted by each of the one or more transmitters.

Described herein are ultra wideband (UWB) receiver systems, and applications thereof. Such a UWB receiver includes a receiver front end and a correlator coupled to the receiver front end. The receiver front end is configured to receive a UWB signal having a plurality of multipath components. The correlator is configured to correlate the UWB signal with a reference signal. The UWB signal includes a plurality of pulses, wherein each pulse has a plurality of multipath components. The reference signal also includes a plurality of multipath components of the pulse. The correlator includes at least one correlator module configured to correlate a plurality of the multipath components of the pulse with the reference signal.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate / sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.