35 results about "Multiple dispatch" patented technology

In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and / or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.

A method of operating a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and / or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.

The invention relates to a method for monitoring and selectively recording the dispatching desks of a digital colony system, in particular to a method for monitoring and recording the dispatching desks of the digital colony system. The method provided by the invention is used for accessing the broadband wireless multimedia information and solves the defect that the hardware resources of the dispatching desks are wasted when the existing dispatching desks record the whole conversation monitoring course. The device for realizing the method comprises one to multiple dispatching desks, a colony dispatching server and multiple user terminals, wherein the dispatching desks for monitoring transmit monitoring request signaling to the colony dispatching server; the colony dispatching server transmits the voice data of a monitored user to the dispatching desks for monitoring; the dispatching desks for monitoring carry out the operation of starting the recording or stopping the recording; and after the monitoring ends, the data base of the dispatching desks for monitoring records the ending time of the conversation, records the conversation time and stores recoding files.