281 results about "Generative Design" patented technology

A method for hierarchical layout of an electronic design using an electronic computer aided design system, wherein the method includes generating a parameterized pattern library and using an existing netlist and analyze in a pattern recognizer, from which a list of associations between the pattern library and the netlist is created. Renesting then occurs wherein the netlist using the list of associations is used for generating a hierarchical layout of the electronic components in the design.

In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI hardware description, verification environment and a development and design tools are generated, thus making it possible to develop a system LSI optimal to an application within a short period.< / PTEXT>

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I / O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and / or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.

The invention discloses a method for generating road design surface information by laser radar scan, which comprises the following steps: a, an airplane or automobile is used for collecting data for a platform-carried laser scanner; b, original laser point cloud is classified to a ground point type and a non-ground point type; c, the point cloud data of the classified ground point types can be used for generating road surface information required by design; d, for regions with the point cloud density of the ground point type less than 4 / m<2>, an alternative point is automatically extracted from the non-ground point type point cloud; e, a sectional profile is taken as a projection surface, the extracted section point, ground point, non-ground point and alternative point are stacked for displaying, artificial auxiliary edit is carried out, in the section ground line, the alternative point is added, or an abrupt abnormal point is removed; and f, accurate section ground line surface information after editing is output according to a format required by the road design. The method of the invention has the advantages of rapidity, high efficiency and high stability; and is suitable for collecting information of construction, reconstruction and extension of various complex road surfaces.

One embodiment provides a method to determine if a pattern is robustly manufacturable. During operation, the system may receive a first pattern and a design intent, wherein the first pattern is intended to generate the design intent. Next, the system may determine a second pattern using the design intent, wherein subjecting the second pattern to a second manufacturing process is expected to generate a third pattern that is substantially similar to the design intent. The system may then determine if a first semiconductor manufacturing process is capable of robustly manufacturing the second pattern. If the second pattern is not robustly manufacturable, the system may generate an indicator that indicates that the first pattern is not robustly manufacturable.

Methods, systems, and apparatus, including medium-encoded computer program products, for facilitating editing of generative design geometry of physical structures, include a method including: receiving editable smooth surface(s), e.g., a T-Spline, constructed from a mesh obtained using a generative design process; instantiating a parametric feature recipe to connect the editable smooth surface(s) with input solid(s), wherein the parametric feature recipe includes an operation sequence that (i) converts the editable smooth surface(s) into boundary representation format and (ii) combines the boundary representation formatted smooth surface(s) with the input solid(s) to produce a watertight three dimensional model of an object; modifying the editable smooth surface(s) in response to input, while preventing disconnection of the editable smooth surface(s) from the input solid(s); updating a visualization thereof in a user interface; and performing the operation sequence of the parametric feature recipe to produce the watertight three dimensional model of the object.

The invention relates to a design method of a reconfigurable embedded system based on the ontology and a system. The method comprises the specific steps as follows: the design method is implemented by a noumenon-based knowledge system which is designed for the application in the embedded system field and an embedded type development platform which is specially developed for the embedded system design. The invention has the advantages that the method greatly shortens the design period, achieves the reuse of design knowledge and solves the problems of the prior art, such as long design period and failure in reuse of design knowledge; the noumenon-based embedded type knowledge system is developed, and the knowledge system is established based on the ontology; the knowledge system has updating and self-learning characteristics and can collect the up-to-date information on the Web network by adding a data acquisition module during the development process of the knowledge system; the embedded type system platform is developed under the guidance of the knowledge system; and according to the design purpose, the knowledge system generates the design plan, and then the design details are manually completed to make the system prefect.

A method and system generates a building design and a three-dimensional image thereof. First building information comprising a length, width, total height and wall height of a building is received via a first graphical user interface. If the length, width, total height, wall height, and a selectable building shape yield a valid set of building parameters, a design of said building is generated at a first software module, which is configured to generate the design, including wall portions and a roof portion, using minimum information consisting of the length, width, total height, wall height, and selectable building shape. A first image and a structural analysis of the design are generated. A second software module generates a second three-dimensional image of the building, which is different from the first image. A second graphical user interface permits a user to modify the second image to include predefined building elements.

A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more nodes of the design. A binary decision diagram for the initial state function of one or more state variables of the design is generated and the design is subsequently initialized. Binary decisions diagrams for one or more constraints are synthesized. A set of constraint values is accumulated over time by combining the binary decision diagrams for the one or more constraints with a set of previously generated binary decision diagrams for a set of constraints previously used in one or more previous time-steps. A binary decision diagram for the next state function of the one or more state variables in the design is constructed in the presence of the constraints. The one or more state variables in the design are updated by propagating the binary decision diagram for the next state function to the one or more state variables and a set of binary decision diagrams for the one or more targets in the presence of the one or more constraints is calculated. The set of binary decision diagrams for one or more targets is constrained and the design is verified by determining whether the one or more targets were hit.