87 results about "Functional description" patented technology

A method and a system for integration of a field device in an installation control system having a communications network and a control station functions in that a field device transmits a functional description of device functions to the control station in a standardized form, whereupon functions associated with the field device are installed on the control station, and communications links are set up between the device functions of the field device and the functions of the control station. In one preferred version of the invention, device functions are automatically or manually combined with an installation structure. The invention is preferably used with high voltage or medium voltage switchgear assemblies and leads to a considerable reduction in the complexity for specification and commissioning of installation internal communications links and to higher quality of a resulting installation control system.

A method for particle beam lithography, such as electron beam (EB) lithography, includes predefining a stencil design having a plurality of cell patterns with information from a cell library, fabricating the stencil design, synthesizing a functional description into a logic circuit design after predefining the stencil design so that one or more characteristics of the stencil design are considered during synthesizing of the functional description into the logic circuit design, optimizing the logic circuit design, generating a layout design from the optimized logic circuit design, and forming the logic circuit on a substrate according to the stencil design and the layout design.

Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and repeatable process for evaluating synchronous circuit designs, converting the wires, switches/connections and logic functions to equivalent-function asynchronous circuit designs and hence implementing a functionally equivalent asynchronous circuit with all the benefits thereof. Further provided are a process for systematically doing the conversion and hardware equivalents (in form or functional description) for the asynchronous components. Using the present invention, any synchronous circuit design can be converted to an asynchronous equivalent, typically with no change to the original design implementation.

According to various illustrative embodiments of the present invention, a method for a content-driven threat management system includes creating a threat detection primary object with threat mitigation data using at least one researcher of at least one of software and malicious code, encoding the threat detection primary object with threat mitigation data within an object capable of being transmitted to a personal computer system using a transmission vector update function, and transmitting the threat detection primary object with threat mitigation data to a threat agent using the transmission vector update function. The method also includes updating at least one threat function using the threat agent to update at least one threat functional description of the at least one threat function to include the threat detection primary object with threat mitigation data, and using the threat detection primary object with threat mitigation data to be capable of recognizing at least one threat event based upon the threat detection primary object with threat mitigation data.

The invention discloses a subject service describing and matching method based on semantic and QoS constraint, which comprehensively considers semantic and QoS attributes and describes and matches the subject service. The invention is composed of processes of subject service describing and subject service matching, wherein, the subject service describing process can carry out general description,functional description and service quality attribute description on the subject service, the subject service matching process can intensively find one or a plurality of subject services satisfying semantic similarity threshold value and featuring the optimal QoS in subject service suppliers according to a subject service requester. The invention can perform comprehensive capacity description on the subject service, comprehensively considers semantic and QoS influences on subject service matching, and objectively and impartially selects one or a plurality of subject services satisfying semantic condition and featuring the optimal QoS according to subject service request, thus solving the problems that service quality and semantics are not well combined, matching effect is not accurate, thematching process is subjective and unfair, etc. in the existing methods.

In the disclosed invention, a module in the functional description is fractionalized according to functions, the functional description is converted into two hierarchies and then the fractionalized modules are rearranged so as to decrease a critical path; and the rearranged modules are grouped to generate an intermediate hierarchy and a logical synthesis and optimization processing and a place and route processing are executed using the functional description after the formation of the intermediate hierarchy.

A display of CPU utilization in a multiprocessor system is provided. This feature illustrates processor utilization and application group assignments to CPUs and clusters of CPUs. Various graphic indicator are described that can be used to display processor utilization and indicate processors that have no application group assignments. For example, bar graphs as well as gauge displays can be used to visually convey processor utilization. As a result, a user can visually determine the processor utilization and application group assignments across a multiprocessor system. Additionally, various colors and shadings can be used to visually convey application group assignments.

A method for including probe locations in an integrated circuit may include specifying probe cells prior to the place and route stage of the design process. The probe cell locations may be specified in a functional description of the integrated circuit, such as an HDL description from which a netlist may be generated. Alternatively, an existing netlist may be edited to include the probe cells on specified nets. The probe locations are included in the physical layout design along with the rest of the integrated circuit components during place and route. The integrated circuit may be fabricated according to the physical layout design so that the fabricated integrated circuit includes the one or more probe locations.

A method, computer readable medium apparatus and system for developing an Application-Specific Integrated Circuit (“ASIC”) are disclosed. In one embodiment, a method includes defining the functionality of a target ASIC device within a target system, as well as synthesizing circuits for the target ASIC device and a programmable logic device concurrently or nearly concurrently, thereby providing a conversion-less ASIC development flow using one or more programmable devices. In a specific embodiment, the conversion-less ASIC development flow requires no subsequent step of modifying a functional description for the target ASIC device from a functional description expressed in terms of the programmable logic device, thereby reducing an amount of time required to produce the target ASIC device.

A testability analysis system analyzes testability by evaluating controllability and observability at the level of a hardware functional description independent of architecture. The testability analysis system comprises: an input part inputting functional description data to define a hardware function; a register variable identifying part identifying register variables whereby memory elements such as a flip-flop in said functional description data are inferred; a random pattern generator applying random patterns to the register variable identified by said register variable identifying part; a simulator conducting a simulation on an event caused by applying the random patterns; and an analysis part analyzing a cause of decrease of a fault coverage by LogicBIST, which is mainly caused by the difficulty of detecting faults by the random pattern test that PRPG (Pseudo Random Pattern Generator) of the Scan-Based LogicBIST executes, based upon toggle rates and simulation events of variables (such as net and bus) in said functional description data in accordance with a result of said simulation.

Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first cell and a second cell. The first and second cell are associated with a functional description of an integrated circuit. A floorplan associated with the functional description is modified to create a modified floorplan. The modified floorplan has a physical design change relative to the floorplan. A pre-route is automatically generated based on receipt of the routing selection and the modified floorplan. The pre-route is added to a physical design of the chip to create a pre-routed physical design. Additional methods and systems are disclosed.