88 results about "Cmos pixels" patented technology

A MOS or CMOS sensor with a multi-layer photodiode layer covering an array of active pixel circuits. The multi-layer photodiode layer of each pixel is fabricated as continuous layers of charge generating material on top of the MOS and / or CMOS pixel circuits so that extremely small pixels are possible with almost 100 percent packing factors. The sensor includes special features to minimize or eliminate pixel to pixel crosstalk. A micro-lens array with a micro-lens positioned above each pixel directs light illuminating the pixel toward the central portion of the pixel and away from its edges. Also, preferably carbon is added to doped amorphous silicon N or P bottom layer of the multi-layer photodiode layer to increase the electrical resistivity in the bottom layer to further discourage crosstalk. In preferred embodiments each of the pixels define a tiny surface area equal to or larger than about 3.24 square microns and smaller than or equal to about 25 square microns. Detailed descriptions are provided for two general types of sensors. The first type has a pixel count of about 0.3 to 1.9 million pixels and are especially suited for sues such as cell phone cameras. The second type with pixel count of between about 1.9 million pixels to more than 5 million pixels is especially suited for high definition television cameras.

An improved CMOS pixel with a combination of analog and digital readouts to provide a large pixel dynamic range without compromising low-light performance using a comparator to test the value of an accumulated charge at a series of exponentially increasing exposure times. The test is used to stop the integration of photocurrent once the accumulated analog voltage has reached a predetermined threshold. A one-bit output value of the test is read out of the pixel (digitally) at each of the exponentially increasing exposure periods. At the end of the integration period, the analog value stored on the integration capacitor is read out using conventional CMOS active pixel readout circuits.

A method for determining a pixel output value of an imager; the imager having a plurality of pixels, a reset switch associated with each pixel and a select switch associated with each pixel; due to incident illumination upon a pixel of the imager after a reset period. The method captures a first pixel output value when the reset switch is OFF during a reset period and the select switch is ON during a reset period and captures a second pixel output value when the select switch is ON near an end of an integration period. If the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period preceding the first integration period and the select switch is ON during a reset period preceding the first integration period. Moreover, if the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period immediately following the first integration period and the select switch is ON during a reset period immediately following the first integration period.

An CMOS active pixel sensor (APS) imaging system include circuitry to compensate for different analog offset levels from the CMOS pixel array. More specifically, the compensation is performed in the analog (charge) domain. A digital correction value, which may be measured as part of the operation or testing of the CMOS APS system, is provided to a offset correction block circuit, to generate an analog electrical signal. The analog electrical signal is supplied to a sample-and-hold circuit including a charge amplifier. The signal read from the pixel array, after conditioning through an analog signal chain, is also supplied to the charge amplifier, which has a linear transfer function and outputs the compensated signal.

An array of multicolor CMOS pixel sensors has a plurality of photosensors per pixel, each photosensor coupled to a single sense node through a select transistor having a select input, each pixel sensor including a reset transistor coupled to the sense node and having a reset input, an amplifier coupled to the sense node and a row-select transistor coupled to the amplifier. The select inputs and the reset inputs for pixel sensors in a pair of adjacent rows are coupled to select signal lines and reset signal lines associated with the pair of rows. The amplifier transistors in individual columns of each row are coupled to a column output line through a row-select transistor having a row-select input. The row-select inputs for pixel sensors in each row of the array are coupled to a row-select line associated with the row.

Mass transfer of micro structures are effected from one substrate to another using adhesives. In the context of an integrated micro LED display, a micro LED array is fabricated on a native substrate and corresponding CMOS pixel drivers are fabricated on a separate substrate. The micro LED substrate (e.g., sapphire) and the CMOS substrate (e.g., silicon) may be incompatible. For example, they may have different thermal coefficients of expansion which make it difficult to bond the micro LEDs to the pixel driver circuitry. The micro LED array is transferred to an intermediate substrate (e.g., silicon) by use of an adhesive. This intermediate substrate may be used in a process of bonding the micro LED array to the array of pixel drivers. The intermediate substrate is separated from the micro LED array by releasing the adhesive.

A frame shuttered CMOS image sensor with simultaneous array readout. An array of CMOS pixels are printed on a silicon substrate. Within each pixel is a light sensitive region comprising a photo sensitive diode for converting photons into electrical charge and at least three transistors to permit reading of reset electrical charges and collected electrical charges and for re-setting the photosensitive diode. The sensor includes an array of signal and re-set readout capacitors located on the substrate but outside of the pixel array. Metal conductors printed in said substrate connect each pixel in said pixel array with a signal capacitor and a re-set capacitor in array of signal and re-set readout capacitors. Transistor switches printed in said substrate but outside of said pixel array are used to isolate the signal and re-set capacitors from each other and from the pixels. Control circuitry is provided for re-setting simultaneously each of the pixels in the pixel array, for collecting simultaneously re-set signals from each pixel on to one of the reset capacitors in the array of readout capacitors and for collecting simultaneously integrated pixel signals from each pixel on to one of the signal capacitors in the array of readout capacitors. Readout circuitry is provided for reading charges collected on the array of signal and re-set capacitors.

A method of operating a CMOS pixel is disclosed. The CMOS pixel includes a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate. A potential barrier is formed between a potential well underlying the PPD and the transfer gate. Charge is accumulated in the potential well in response to electromagnetic radiation during a first integration time. Excess charge is removed from the potential well to the anti-blooming drain that exceeds the first potential barrier. A size of the potential barrier is increased. Charge is accumulated in the potential well during a second integration time.