1734results about "Signal processing using self-clocking codes" patented technology

Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.

A digital modulator which inputs a data stream to convert to a channel bit stream. The multiplexed data block is generated by multiplexing dummy data to any position within each data block cut out of the data stream one by one. The first Reed-Solomon code is generated by Reed-Solomon-encoding the multiplexed data block as an information part. A plurality of second Reed-Solomon codes are generated by adding a plurality of Reed-Solomon codes for scrambling each of which has identification data showing its scrambling pattern in the same position as that of the dummy data, and the code length of information part and parity part is the same as the first Reed-Solomon code. The second Reed-Solomon code in which the characteristics becomes desirable after modulation among the plurality of the second Reed-Solomon codes is set for output.

Techniques for detecting data, such as servo data, from input or incoming data read from a transmission medium, such as magnetic recording medium, in the presence or absence of radial incoherence. In one illustrative recording medium-based aspect of the invention, such a technique for detecting data from input data stored on a recording medium comprises the following steps. First, one or more samples are interpolated from one or more samples which have been generated from the input data at a given symbol rate. The one or more interpolated samples have one or more phases associated therewith which differ from a phase associated with the one or more samples generated at the given symbol rate. Then, an optimum or best phase is selected from the symbol rate phase and the one or more interpolated phases such that at least a portion of the one or more samples associated with the optimum phase are identified as representative of detected data.

A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

A partial response (PR) waveform generator generates a digital value sequence of an expected PR waveform based on the output of a soft-decision Viterbi detector included in, for example, a first-stage decoder unit incorporated in an iterative decoder. The generator also generates flag information indicative of whether reliability of the digital value sequence is low or high, in parallel with the generation of the digital value sequence. An error detector detects error values in a PR equalized sample value sequence, needed for feedback control of a control target, using the digital value sequence of the expected PR waveform as a digital value sequence of a reference waveform. An error output controller controls the output of the error values detected by the error detector in accordance with the state of the flag information generated by the generator.

Various embodiments of the present invention provide systems and methods for selecting between pre-coding and non-pre-coding. As an example, a data processing circuit is disclosed that includes: a first data detector circuit, a second data detector circuit, a first comparator circuit, a second comparator circuit, and a pre-code selection circuit. The first data detector circuit is selectably configurable to operate in a pre-coded state, and operable to apply a data detection algorithm on a data input to yield a first detected output. The second data detector circuit operable to apply the data detection algorithm to the data input to yield a second detected output without compensating for pre-coding. The first comparator circuit operable to compare the first detected output against a known input to yield a first comparison value, and the second comparator circuit operable to compare the second detected output against the known input to yield a second comparison value. The pre-code selection circuit is operable to determine a selectable configuration of the first data detector circuit based at least in part on the first comparison value and the second comparison value.

Synchronized data is written to magnetic tape while reducing the number of backhitches. A controller detects a pattern of synchronizing events for received data records to be written to tape; writes each transaction of data records to the magnetic tape; accumulates the synchronized transactions in a buffer; and subsequently recursively writes the accumulated transactions of data records from the buffer to the magnetic tape in a sequence. A single backhitch may be employed to place the recursively written accumulated data records following the preceding data, maximizing performance and capacity.

A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent before implementing a data transfer, a delay value with which the starting edge and ending edge of the data match the rising edge of the clock is found for the variable delay circuit, and a delay value with which the transfer data can be received in a stable manner is set based on the delay value of the variable delay circuit.

An optical disk read signal processing system for Blu-ray disc systems to ensure stable phase-locked locked operation even with a low signal-to-noise ratio. This system changes a loop configuration of a phase lock loop circuit according to the operating state, and utilizes a FIR equalizer for phase detection. This system attains a low error rate even when the signal-to-noise ratio of an input signal is low, and avoids pulse edges with low phase detection accuracy or signal pulse streams with a high possibility of being mistakenly detected as an edge in conventional methods, and also supports diverse types of input signals.

Methods, circuits, and systems for processing a preamble field in a read channel (e.g., in a magnetic storage device such as a hard disk drive). The methods generally include the steps of (a) reading the preamble field, wherein the preamble field comprises a repetitive bit pattern having a logical transition every x bit periods, where x is an integer of at least 3 when d is 0 or 1, or where x is an integer of at least d+2 when d is greater than 1, and (b) processing the repetitive bit pattern. The methods may further relate to processing the preamble for synchronization with the read channel and/or for measuring the fly height of a read/write head. The invention also relates to methods of enabling read channel synchronization and/or fly height measurement. The circuitry for fly height measurement generally includes (a) reading logic configured to read a preamble field from a read channel, wherein the preamble field comprises a repetitive bit pattern, (b) determination logic configured to determine a characteristic of the repetitive bit pattern, and (c) correlation logic configured to correlate the characteristic to the fly height. The systems generally comprise those that include a circuit embodying one or more of the inventive concepts disclosed herein. The present invention advantageously provides improved resolution of signals resulting from the preamble fields and of harmonics of said signals, and enables fly height measurement and improved channel synchronization without consuming dedicated tracks, platters, etc. on a magnetic recording medium.

Plural grooves or lands formed in an information recording carrier include at least a wobbling region and data is recorded wobblingly in this wobbling region by frequency shift modulation while recorded digitally with a single or multiple waves as a channel bit.