71results about "Logic circuits coupling/interface with bidirectional operation" patented technology

A circuit for shifting a level between two bidirectional signals having different voltage levels. The circuit includes a first analog switch including a first switching control terminal connected to first directional signal stage, a first input terminal connected to a first level of operating voltage, and a first output terminal connected to a second directional signal stage, for performing a switching operation for the first input terminal and the first output terminal based on a state of logic level of a signal from the second directional signal stage. The circuit also includes a second analog switch including a second switching control terminal connected to the first directional signal stage, a second input terminal connected to a second level of operating voltage, and a second output terminal connected to the first directional signal stage for performing a switching operation for the second input terminal and the second output terminal based on a state of a logic level of a signal from the first directional signal stage.

A bidirectional buffer circuit includes a first terminal, a second terminal, a first output buffer to which a signal from the first terminal is input and which outputs the signal to the second terminal, a first one-shot buffer control circuit outputting a first control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, a first one-shot buffer temporarily driving the second terminal by the first control signal, a second output buffer to which a signal from the second terminal is input and which outputs the signal to the first terminal, a second one-shot buffer control circuit outputting a second control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, and a second one-shot buffer temporarily driving the first terminal by the second control signal.

A wire used for transferring bidirectional signals is divided into a plurality of sub line segments. These sub line segments are classified into groups. Further, bidirectional buffers are provided between respective adjacent sub wires. The direction of transfer of a signal by each of the bidirectional buffers is controlled based on at least one of control signals used to control drivers for respectively outputting data signals to the sub line segments.</PTEXT>

The invention provides a bidirectional level conversion circuit and a bilateral level conversion chip. The bilateral level conversion circuit comprises a signal transmission tube, a first pull-up tube, a second pull-up tube and a pull-up control module; a first end of the first pull-up tube is electrically connected with a first voltage end, a second end is electrically connected with the first end of the signal transmission tube; the first end of the second pull-up tube is electrically connected with a second voltage end, and the second end is electrically connected with a second end of the signal transmission tube; a first signal input end of the pull-up control module is electrically connected with the first end of the signal transmission tube, a second signal input end is electricallyconnected with the second end of the signal transmission tube, and an output end is electrically connected with grids of the first pull-up tube and the second pull-up tube and used for outputting first level pulse when any one end of the first end and the second end of the signal transmission tube is overturned as the second level from the first level. Two pull-up tubes in the conversion circuit is controlled by one pull-up control module, the module amount and the design complexity can be reduced, and the chip area and cost can be reduced.

The invention discloses a communication isolation and level switching circuit. The communication isolation and level switching circuit is separately connected with a battery and a host, and comprises a first branch and a second branch; the first branch comprises a diode D1, a pull-up resistor R1 and a pull-up resistor R3; and the second branch comprises an audion Q1, an audion Q2, a pull-up resistor R8 and a pull-up resistor R10. By means of the communication isolation and level switching circuit disclosed by the invention, the communication function between MCUs having different power supply voltage can be solved; and the problem that the battery can be damaged due to the fact that high voltage of the host is supplied to the battery when the host is abnormal can be prevented.

The invention discloses a level translation circuit. The circuit comprises a first phase inverter, a second phase inverter, a third phase inverter, a first NMOS tube, a second NMOS tube, a third NMOStube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first PMOS tube, a second PMOS tube, a primary NPN tube set, a third PMOS tube, and a fourth PMOS tube, wherein the primary NPN tube set comprises a first NPN tube and a second NPN tube. The level translation circuit can enable working points of all MOS tubes to not exceed the breakdown voltage thereof when the external power voltage of the level translation circuit exceeds the breakdown voltage of the internal MOS tube, thereby enabling the circuit to work in the safety working voltage range; the required level translation performance can be guarantee, and the circuit reliability can be improved to guarantee the normal work of the circuit.

The invention discloses a power supply power-on module. The power supply power-on module is used for controlling the on-off state of digital I/O. The power supply power-on module is characterized by comprising a VDDC power supply, a VDDIO power supply, a pull-down MOS transistor N1, a first transmission MOS transistor P1, a second transmission MOS transistor P2 and a time delay unit, the grid electrode of the pull-down MOS tube N1 is connected with the VDDC power supply, the source electrode of the pull-down MOS tube N1 is grounded, and the drain electrode of the pull-down MOS tube N1 is connected with a node A; source electrodes of the first transmission MOS tube P1 and the second transmission MOS tube P2 are simultaneously connected with the VDDIO power supply, drain electrodes of the first transmission MOS tube P1 and the second transmission MOS tube P2 are respectively connected with a node A and a node B, grid electrodes of the first transmission MOS tube P1 and the second transmission MOS tube P2 are respectively connected with the node B and the node A, and the node A and the node B are mutually reverse signals. And the node B is connected with a control signal FP. Accordingto the power supply power-on module provided by the invention, the generated control signal FP can correctly open or close the digital I/O, so that electric leakage of the digital I/O can be avoided,and electric leakage of the power supply power-on module in the prior art is also avoided.

The invention discloses an inductive coupling isolator, which comprises: a coupling inductor pair; a first encoding and decoding circuit which is used for transmitting first data to a second encodingand decoding circuit through the coupling inductor pair when a first starting signal is received, wherein when a first termination signal is received, sending the first data to the second encoding anddecoding circuit is stopped, and a non-isolated side controller is notified to prepare to send the second data; and a second encoding and decoding circuit which is used for receiving the first data,notifying the non-isolated side controller to prepare to send second data when receiving the first termination signal, and transmitting the second data to the first encoding and decoding circuit through the coupling inductor pair, wherein when a second termination signal is received, sending the second data to the first encoding and decoding circuit is stopped, and an isolation side controller isnotified to send the data of the next period by using the second termination signal. Only one coupling inductor pair is used in the isolator, so that the space volume occupied by the inductive couplercan be reduced.

The invention discloses an automatic direction detection circuit of a bidirectional transmission interface. The automatic direction detection circuit comprises a D trigger, a primary NAND gate and a final NAND gate which are configured corresponding to signal input and output on any side, a pre-driving signal is accessed to the D end of the D trigger; an input signal is accessed to a Clk end of the D trigger; the Q end of the D trigger outputs enable signals on the corresponding side sequentially through the primary NAND gate and the final NAND gate, the detection circuit is provided with periodic reset units connected to the Reset end of the D trigger based on input signals on the two sides, and the output ends of the primary NAND gates on the two sides are connected to one input end of the primary NAND gate on the other side in a jumper mode. By applying the detection circuit design, whether the output of the side is opened or not can be periodically detected through the rising edgeor the falling edge of the input side signal, and the enable signal can be reset; hardware loss of automatic direction recognition is greatly reduced, and flexibility of automatic direction recognition is improved.

The invention discloses a low cost repeatable trimming method applied to an integrated circuit; the method comprises the following steps: S1, using a switch to reuse two input pins of an operational amplifier, and using a switch control signal to open and close the switch through trimming pads P1; S2, adding shift registers of the same number according to the trimming bit number, and reusing positive/negative input pins of the operational amplifier to provide a clock signal and a data signal of the shift register; S3, adding a control circuit of signals B0-B4. The method only needs two trimming pads to trim all bits, thus saving a chip area; the method can repeatedly repair; if errors happen in the trimming process, the trimming process can be restarted; the method only needs to trim 4 times to reach the user needed trimming precision no matter how many bits need to be trimmed, thus greatly reducing trimming testing time and trimming cost.