30 results about "Phased logic" patented technology

A device for generating a pair of true / complementary-phase logic signals is provided. The device comprises a single-end to true / complementary-phase signal conversion circuit, a first stage circuit and a differential amplifier. The conversion circuit receives a single-end signal and converting the single-end signal to a first pair of true / complementary-phase signals. The first stage circuit receives the first pair of true / complementary-phase signals and performing a feedback control to obtain a second pair of true / complementary-phase signals. The differential amplifier receives the second pair of true / complementary-phase signals and outputs a pair of differential signals. Therefore, the rising time / falling time of one of the pair of differential signals is synchronized with the falling time / rising time of the other of the pair of differential signals.

Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

A device for generating a pair of true / complementary-phase logic signals is provided. The device comprises a single-end to true / complementary-phase signal conversion circuit, a first stage circuit and a differential amplifier. The conversion circuit receives a single-end signal and converting the single-end signal to a first pair of true / complementary-phase signals. The first stage circuit receives the first pair of true / complementary-phase signals and performing a feedback control to obtain a second pair of true / complementary-phase signals. The differential amplifier receives the second pair of true / complementary-phase signals and outputs a pair of differential signals. Therefore, the rising time / falling time of one of the pair of differential signals is synchronized with the falling time / rising time of the other of the pair of differential signals.

A scan driving device with N numbers of displacement working-storage is prepared as coupling the first input end of inverse-OR gate to input not and it's the second input end to output node, using switch-element to receive output signal of inverse-OR gate to decide whether to connect trough circuit between two said ends or not, coupling input end of the first reversed phase logic gate to the second end and its output end to output node, using the first input node to receive initial signal and odd first end to receive scan signal as well as even first end to receive reversed phase signal of scan signal.

A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock frequency, and n includes an integer greater than 1. The device includes a phase logic signal generator for generating a phase logic signal from the two clock signals by assigning a predetermined logic value to the phase logic signal when a rising edge of the fast clock signal matches a predetermined location of the slow clock signal.

The invention provides a power management chip, which includes: a phase logic voltage unit, at least three integrated power management units and multifunctional configuration pins. The power management chip is applied to a step-down power conversion circuit. When configured as a parallel output, multiple integrated power management units connected in parallel are controlled by the phase logic voltage unit to supply power for the same load in parallel, wherein each integrated power management unit can also be Configured as an independent working mode, the present invention satisfies the demands of high-power loads by controlling the integrated power management unit in different working modes and different application conditions. In addition, the power management chip has flexible configuration and simple peripheral structure, and can meet the requirements of miniaturization, portability, and lightweight transformation.

The invention discloses an implication type solid-phase logic gate based on BSA (bull serum albumin) / 3-MPA (mercaptopropionic acid)-gold nanocluster-polyelectrolyte and a construction method of the implication type solid-phase logic gate. On the basis of the phenomenon that H+ can inhibit fluorescence quenching of Fe2+ to a BSA / 3-MPA-gold nanocluster-polyelectrolyte solid-phase compound in an acetic acid buffer solution with the pH value of 4.6, the Fe2+ and the H+ are taken as input signals, the gold nanocluster-polyelectrolyte solid-phase compound serves as a signal converter, and an implication type solid-phase logic gate system is created. The logic gate system has the advantages of simplicity and convenience in operation (without any modifying and marking processes), high transferability, capability of being reset, diversification in signal reading and the like, and has good application prospect in the fields of clinical diagnosis, chemical sensing, environment monitoring and the like.

The invention discloses a self-starting electric control device, a single-phase permanent-magnet motor and a self-starting electric control method. The self-starting electric control device comprises a power supply switch, a rectification module and a power supply phase logic judgment module, wherein the power supply switch is connected with a power supply and a main phase winding of the single-phase permanent magnet motor respectively and is connected with a secondary phase winding of the single-phase permanent magnet motor by a running capacitor so as to respectively control whether the power supply provides power for the main phase winding and the secondary phase winding or not, the rectification module is connected between the power supply switch and the secondary phase winding so that a d axis of a rotor of the single-phase permanent magnet motor is coincided with an axial line of the secondary phase winding, the power supply phase logic judgment module is connected with the power supply and communicates with the power supply switch, and when the d axis of the rotor is coincided with the axial line of the secondary phase winding and the power supply phase logic judgment module judges that a power supply phase is matched, the power supply switch controls the power supply to simultaneously supply power to the main phase winding and the secondary phase winding and also disconnect independent power supply to the secondary phase winding. The self-starting electric control device disclosed according to the invention has the advantages of high reliability and high starting success rate.

The invention relates to the field of multiple-spray-head ink-jet printers and provides a phase different electronic calibration system of multiple-spray-head printing spray points. The phase different electronic calibration system of the multiple-spray-head printing spray point comprises a main board, a phase logic processing unit, a first asynchronous first in first out (FIFO), a second asynchronous FIFO, a first driving circuit, a second driving circuit, a first spray head and a second spray head. By adopting an electronic calibration technology, machine calibration difficulty is reduced, and mechanical calibration mechanism is simplified. A spray head dolly direction signal is used for judging positive and negative of phase, thereby reducing complexity of the phase logic processing unit and simultaneously improving the reliability. Phase transmission is shown by adopting pulse width, thereby improving flexibility and reliability of the main board controlling phase different between the two spray heads. By means of separation of the phase logic processing unit and the main board, original main board design is retained ingeniously, development cost is reduced, and development progress is accelerated. The number of signals of the main board and the spray head driving circuits is decreased, the cost is reduced, and the signal sending reliability of the main board is improved.

The invention provides a delay locked loop, comprising: a digitally controlled delay chain, which adjusts the delay of the digitally controlled delay chain, and outputs a clock signal in a corresponding output mode; a phase detection logic circuit, according to the reference clock and Whether the delay difference of the feedback clock falls within the locking accuracy range Generate and output the lead or lag signal, lock logic signal; digitally control the delay chain control code generation circuit, and initially generate the rough delay chain control code according to the cycle size of the reference clock , then generate said other fine-tuning delay chain control codes according to the delay difference between the reference clock and the feedback clock, and finally adjust the fine-tuning delay chain control codes according to the lead or lag signal; the multi-mode selection control circuit, according to the working mode The selection signal control circuit is in a corresponding working mode, and at the same time combined with the locking logic signal to control the multi-mode selection control circuit to generate and output the first-bit fine-tuning delay chain control code in the corresponding working mode.

A scan driving device with N numbers of displacement working-storage is prepared as coupling the first input end of inverse-OR gate to input not and it's the second input end to output node, using switch-element to receive output signal of inverse-OR gate to decide whether to connect trough circuit between two said ends or not, coupling input end of the first reversed phase logic gate to the second end and its output end to output node, using the first input node to receive initial signal and odd first end to receive scan signal as well as even first end to receive reversed phase signal of scan signal.

The invention discloses a circuit breaker having a zero-line disconnection and open-phase protection function. The circuit breaker comprises a circuit element including a three-phase line inlet wiring terminal, a three-phase line outlet wiring terminal, a zero line inlet wiring terminal, a zero-line outlet wiring terminal, a circuit breaker, three capacitors, a zero-sequence differential voltage relay, a current transformer, a current relay, a zero-line disconnection logic judgment module, a zero line disconnection signal relay, three low-voltage relays, an open-phase logic judgment module and a phase failure signal relay. In addition, the invention also discloses a circuit break system having a zero-line-breaking and open-phase protection function. With the circuit breaker and the circuit break system, the zero-line-breaking and open-phase detection function is realized. With the tripping protection way, losses caused by zero-line disconnection and open-phase running can be effectively reduced; and thus the personal and property safety of users can be protected.

The invention discloses a clock recovery circuit and method, a data processing chip and electronic equipment. The clock recovery circuit comprises a latch module, a monostable module and an anti-phase logic unit, wherein a first setting end S of the latch module inputs multiple groups of pulse signals, and when any group of pulse signals jumps from a low level to a high level, a latch rises and is output through a first output end; the input end of the anti-phase logic unit is coupled with the first output end of the latch module, the first output end of the anti-phase logic unit is coupled with the first reset end RN of the latch module, and the second output end of the anti-phase logic unit is coupled with the second set end SN of the latch module; the first input end of the monostable module is coupled with the first output end of the anti-phase logic unit , the second input end of the monostable module inputs a voltage power supply, and the output end of the monostable module is coupled with the second reset end R of the latch module; and the input signal of the first reset end RN is opposite to the input signal of the second reset end R. According to the scheme, accurate clock recovery can be realized.

The invention discloses an NOR solid-phase logic gate based on a gold nanocluster-polyelectrolyte compound. On the basis that Fe<2+> and Fe<3+> can induce fluorescence of bovine serum albumin-3-mercaptopropionic acid-gold nanocluster-polyelectrolyte solid-phase compound to be quenched under the condition of coexistence of an acetate buffer solution with the pH being 4.6, an NOR type solid-phase logic gate system is built by using the Fe<2+> and the Fe<3+> as input signals and using the gold nanocluster-polyelectrolyte compound as a signal converter. The logic gate system has the advantages that the operation is simple and convenient (any modification and marking processes are not needed); the transplanting performance is good; the relocatability is realized; the signal reading diversification is realized, and the like. Good application prospects are realized in the fields of clinic diagnosis, chemical sensing, environment monitoring and the like.

The invention provides an integrated circuit and a method and system for adjusting an integrated circuit clocked signal, which comprises a plurality of skew-programmable clock buffer, a fixed phase logic unit, an external interface and a skew controller. Each skew-programmable clock buffer is used for receiving a distributing clocked signal to provide a corresponding local clock signal with a programmed skew. The fixed phase logic unit enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. When using the invention by laser, the best area clock skew of the element can be detected when detecting one element to reach maximum clock speed of the element.

The invention discloses a method for suppressing leakage current of a three-phase four-arm Z-source inverter, which comprises the steps of: comparing three-phase symmetrical sine waves with triangular carrier waves with a phase difference of 120° to obtain three-phase A, B, and C Logic signal; XOR the logic signals of the three phases A, B, and C to obtain the D-phase logic signal; according to the area where the modulating wave is located, select a specific carrier and compare it with the positive and negative through voltage signals to obtain the through control signal; A, B The logic signals of the four bridge arms , C, and D are phase-ORed with the through signal to obtain the control signal of the final switching tube. In the present invention, no matter what mode the circuit is in, the common-mode voltage remains constant, so that the leakage current is controlled within the allowable range. Moreover, the modulation method does not have a complicated calculation process and is easy to implement.