994 results about "Multi state" patented technology

The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” element to minimize the number of sequential verify operations for each program / verify / lockout step of the write sequence. In an exemplary embodiment of the write sequence for the multi-state memory during a program / verify cycle sequence of the selected storage elements, at the beginning of the process only the lowest state of the multi-state range to which the selected storage elements are being programmed is checked during the verify phase. Once the first storage state is reached by one or more of the selected elements, the next state in the sequence of multi-states is added to the verify process.

The present invention is directed to systems and methods for monitoring performance of a variety of activities, preferably including swimming, in a number of states. The invention may comprise an analytics application, a primary device and, optionally, one or more secondary devices or third-party devices for sensing characteristics of the performance of an activity or the environment in which it is performed. The devices are worn during the performance of the activity and contain sensors, preferably accelerometers, for sensing information pertaining to the performance of one or more activities. The information sensed may be provided to a user in the form of real-time feedback and / or made available for long-term analytics and tracking.

A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read / write registers of the non-volatile memory circuit, and then written from the read / write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read / write registers and performing a multi-state programming operation of the portions of the data from the read / write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.