150 results about "Memory form" patented technology

A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die.

The present invention aims at providing a portable radio communication apparatus in which forming of a message is easy. The portable radio communication apparatus is provided with a novel pre-message memory formed of a ROM or the like stored in which are fixed messages each consisting of fixed statements or fixed words as “CALL OFFICE AT XX:XX”. A transmitting message may be readily formed by selecting any of the fixed messages.

A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when the task identifier in the tag and the value of the task register do not coincide.

A vertical split gate memory formed in a trench of a semiconductor substrate comprises a first doping region, a second doping region, a conductive line, a conductive spacer and a conductive plug, wherein the conductive line, conductive spacer and conductive plug serve as a select gate, a floating gate and a control gate of the vertical split gate memory cell, respectively. The first doping region of a first conductive type is underneath the bottom of the trench, whereas the second doping region of the first conductive type is beside the top of the trench. The conductive line serving as the select gate is formed at the bottom of the trench and in operation relation to the first doping region. The conductive spacer is formed beside the sidewall of the trench and above the conductive line. The conductive plug is insulated from the conductive spacer and the conductive line and in operation relation to the conductive spacer.

An apparatus and method for writing and / or reading data in an image processing system are provided. The apparatus for writing data includes: a memory formed with at least one or more banks capable of being accessed independently; and a memory control unit controlling so that a luminance component, a first chrominance component and a second chrominance component belonging to one macroblock are written based on respective structures different to each other, in the memory. The apparatus for reading data includes: a memory formed with one or more banks capable of being accessed independently in which a luminance component, a first chrominance component, and a second chrominance component belonging to one macroblock are written based on respective structures different to each other, in each bank of the memory; and a memory control unit controlling so that a luminance component, a first chrominance component, and a second chrominance component required are read from the memory.

A processor, connected to a non-volatile memory storing first memory authentication information for authentication of the non-volatile memory, the processor includes an operation unit configured to perform an operation utilizing information stored in the non-volatile memory; an authentication memory formed integrally with the operation unit, and storing second memory authentication information for authentication of the non-volatile memory; an authentication information acquiring unit configured to acquire the first memory authentication information from the non-volatile memory; a memory authenticating unit configured to compare the first memory authentication information and the second memory authentication information to authenticate the non-volatile memory; and a memory access controlling unit configured to permit an access to the non-volatile memory when the memory authenticating unit succeeds in authentication.