36 results about "Feed forward equalization" patented technology

Systems and methods of mitigating precursor ISIs for communication channels having time-variant precursor channel responses using digital circuit designs. A phase adaptation circuit is utilized in a receiver and configured to generate a phase control signal responsive to an input signal and based on the current precursor channel response. The phase control signal controls the phase shift of a recovered clock to a position where the precursor ISI at h(−1) is minimized. The phase control signal corresponds to a “feed-forward equalization (FFE) first tap weight” obtained via a digital least-mean-square (LMS) process.

Embodiments are disclosed for equalizing input signals for communication systems. An example method includes receiving an input signal. The input signal encodes a plurality of bits in a number of amplitude levels. The example method further includes converting the input signal to an equalized output signal using a plurality of lookup table circuits. The equalized output signal encodes a plurality of symbols in a number of amplitude levels. The example method further includes feeding the equalized output signal to an output driver circuit.

A signal processing system includes an AGC and pre-echo cancellation system for receiving an analog signal, amplifying signal magnitude (over all frequencies) to a pre-determined level by AGC, and removing the immediate transmit pulse from this received signal by pre-echo canceller to provide a second analog signal. The signal processing system also includes a summer for receiving the analog signal; a feed forward equalization (FFE) unit for receiving a signal from the summer; and a slicer for receiving a signal from the FFE unit and providing an output signal. The signal processing system also includes an Echo and NEXT or FEXT cancellation system for receiving the output signal and for providing a signal to the summer for canceling the echo and crosstalk in the signal processing system. The Echo and crosstalk components associated with a signal processing system can be subtracted prior to the FFE.

In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

Methods and systems for a distributed Mach-Zehnder Interferometer (MZI) with an integrated feed forward equalizer (FFE) may include a photonic chip comprising an optical modulator having diode drivers, local voltage domain splitters, and delay elements, where each is distributed along a length of the optical modulator. Outputs of the delay elements may be coupled to inputs of the local domain splitters, and outputs of the local voltage domain splitters may be coupled to inputs of the diode drivers. A feed forward equalization (FFE) module comprising a configurable delay element with inverted outputs coupled to one of the delay elements along the length of the modulator, may be coupled to a local voltage domain splitter. An input electrical signal may be received and delayed using the delay elements and coupled to the local domain splitters, and input electrical signals for the diode drivers may be generated using the local domain splitters.

Embodiments of the present disclosure provide methods and apparatus for providing feed forward equalization to a communication line by providing a resistance and a capacitance to the communication line. The method includes determining the resistance based on a desired value of feed forward equalization to provide to a communication line, determining the capacitance based on the desired value of feed forward equalization to provide to the communication line, providing a layer of resistive material between a first conductor and a second conductor of the communication line, wherein a dimension of the layer of resistive material is determined based on the determined resistance and providing a layer of dielectric material between the first conductor and the second conductor, wherein a dimension of the layer of dielectric material is determined based on the determined capacitance.

The invention provides a low power receiver with a continuous time linear equalizer (CTLE) based on feed forward equalization (FFE). The FFE CTLE comprises: an input for receiving an input signal; a first main path is operably coupled to the input and includes a source follower transistor arranged to apply a scaling factor to a received input signal; the second path is operably coupled to the input and includes a delayer arranged to delay the received input signal and a common source transistor arranged to apply a scaling factor to the delayed received input signal, where the source follower transistor and the common source transistor are connected as a single SF-CS stage, the output of the common source transistor is arranged to subtract the output of the common source transistor from the output of the source follower transistor.

An information handling system communicates information across a physical link with high and low signal values sent at a unit interval. Feed forward equalization improves signal transfer with pre-emphasis of low-to-high signals and de-emphasis of high-to-low signals lasting for a fraction of the unit interval, such as one-half or one-quarter of the unit interval. Fractional unit interval pre-emphasis and de-emphasis reduce inter symbol interference to improve frequency domain eye structure at the physical link receiver.

The present invention relates to a feedforward equalization pre-emphasis circuit, a processing method and a USB driver. The circuit comprises: a first-stage amplifier (101), a voltage dividing filter network (102), a delay unit (103), a second-stage amplifier (104), and a pre-emphasis summing circuit (105). The first-stage amplifier (101) is used for amplifying an amplitude of an input signal and outputting a signal; the voltage dividing filter network (102) is used for carrying out filtering, voltage division and outputting on the signal output by the first-stage amplifier (101); the delay unit (103) is used for delaying the signal output by the voltage dividing filter network (102) and outputting the delayed signal; the second-stage amplifier (104) is used for amplifying and recovering the signal output by the delay unit (103); and the pre-emphasis summing circuit (105) is used for receiving the signal output by the first-stage amplifier (101) and the signal output by the second-stage amplifier (104), carrying out the pre-emphasis summation operation and outputting an operation result. The signal is subjected to pre-emphasis processing at an input terminal so as to avoid the problem of data loss caused by intersymbol interference of the signal in the communication channel transmission process, thereby well ensuring communication quality.