Low power receiver with equalization circuit, communication unit and method thereof

Abstract

The invention provides a low power receiver with a continuous time linear equalizer (CTLE) based on feed forward equalization (FFE). The FFE CTLE comprises: an input for receiving an input signal; a first main path is operably coupled to the input and includes a source follower transistor arranged to apply a scaling factor to a received input signal; the second path is operably coupled to the input and includes a delayer arranged to delay the received input signal and a common source transistor arranged to apply a scaling factor to the delayed received input signal, where the source follower transistor and the common source transistor are connected as a single SF-CS stage, the output of the common source transistor is arranged to subtract the output of the common source transistor from the output of the source follower transistor.

Description

technical field [0001] The field of the invention relates to a low power receiver equalization circuit, a communication unit and a method thereof. In particular, the field of the invention relates to continuous-time linear equalization implementations for high-speed serial links and wired transceivers. Background technique [0002] The main focus and application of the invention is in the field of low power receivers that can be used in receiver equalization circuits, which can be used in high speed serial links and wired transceivers. As total Internet bandwidth increases year by year, data centers require equipment with higher bandwidth to be able to transmit and receive data within the data center. Due to the nature of the wired channel between the transmitting and receiving integrated circuits ("chips"), frequency equalization is required on the receiving side to compensate for channel loss, channel bandwidth limitations, which are often referred to as "insertion loss" ...

AI Technical Summary

Problems solved by technology

[0003] Typical data rates of 56Gbits / sec (Gb / sec) or 56Gsymbols / sec (symbols / sec) would require circuit designs to support an example Nyquist frequency of approximately 28GHz, where it is known that at approximately 28GHz data rates The exact equalization at

[0009] Therefore, there are many known equalization techniques based on CTLE, but all known techniques cannot be used at the data rate of 10+GHz delay line design because they do not perform well at high frequencies (for example, around 28GHz) or because they require multiple adders and buffer stages consume a lot of power

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