36 results about "Display Serial Interface" patented technology

The present invention describes a method and system for interfacing a plurality of device controllers to an array of data storage devices by serial connection. The device controllers are coupled to a serial interface by a bus and the devices of the storage array are coupled to the serial interface by a serial connection. The serial interface receives controller signals through the bus and multiplexes the signals onto the serial connections of the storage array. Arbitration between the various device controllers seeking access to the storage array is resolved through bus protocol and through drive based reserve / release registers in the serial interface processor.

A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.

A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal.

A system on chip includes a display serial interface (DSI) host device, a camera serial interface (CSI) host device, a first register, and a loopback control circuit. The first register is configured to store a first flag indicating whether the system on chip is operating in a loopback mode or a non-loopback mode. The loopback control circuit is configured to loop back data generated by the DSI host device to the CSI host device in response to the first flag indicating that the system on chip is operating in the loopback mode.

Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.

The invention relates to an FPGA (Field Programmable Gate Array) based serial interface and PWM (Pulse Width Modulation) combined application IP (Intellectual Property) core. The FPGA based serial interface and PWM combined application IP core comprises a serial interface module, a PWM module and a connection module; the serial interface module is connected with the PWM module through the connection module; input data are received through the serial interface module; the input data are converted into timing data and duty ratio data through the connection module after calculation to be transmitted to the PWM module; PWM waves are output through the PWM module according to the timing data and the duty ratio data. Compared with the prior art, the operation is convenient, FPGA resources are saved, the user configurability is good, and the like.

Variable rate display interfaces are disclosed. In an exemplary aspect, a high-speed reverse data transfer is enabled over plural lanes of a display serial interface (DSI) bus during blanking periods. Further increases in bandwidth of each high-speed reverse data transfer may be achieved by increasing DSI clock speed during the blanking periods. Since a display relies on a host clock to send reverse data, the frequency of the reverse data is increased, which effectively increases the bandwidth of reverse channel lanes. By increasing the reverse bandwidth over existing pins in the DSI bus, more data may be transferred to the host, including raw touch / stylus data rather than processed data. The raw data may then be processed by the host's relatively powerful processors. By shifting the processing to the host, the need for a powerful touch screen controller (TSC) and / or a powerful touch display driver integrated circuit (TDDI) may be avoided.

The invention discloses a method and a device for simulating a serial interface through GPIO (general purpose input output) based on a windows platform. The method comprises the following steps: acquiring a serial interface command of application software; acquiring a level sequence corresponding to the serial interface command according to a preset serial interface level sequence; calling a windows kernel driver function to access a GPIO port according to the level sequence. According to the method and the device disclosed by the invention, the serial interface command is converted into the level sequence of GPIO, and access of the GPIO port is realized on the windows kernel, so that the serial interface is simulated by the GPIO port under the windows platform, the serial interface equipment is controlled without using an external chip, and the cost of the chip is reduced. Multiple serial interfaces can be simulated by virtue of software simulation, and when the multiple serial interfaces are needed, multiple external chips are not needed, and the hardware cost is greatly reduced.

The invention discloses an information processing method, for solving the technical problem that an electronic apparatus is limited in information processing and storing capabilities. The method comprises the steps of receiving a first operation; and displaying the first display interface of a first application according to the first operation, wherein the first display interface comprises recorded information of voice communication implemented by the first application and keyword information corresponding to the content of the voice communication, and the recorded information is used for indicating the voice communication. The invention also discloses a corresponding electronic apparatus.

The invention discloses a universal data transmission system, comprising a computer host and at least one data transmission device, wherein the computer host is configured with at least one display interface. The computer host is connected with the data transmission device by the display interface. The computer host is mainly used for transmitting high-speed transmitted data to the data transmission device through the display interface according to transmission rate requirements of the data transmission device. The data transmission device receives the data transmitted by the computer host at high speed, and converts the data to be data form required by external equipment which is connected with the data transmission device and outputs the data. In the technical scheme of the invention, a graphics card or an accelerated processing unit having graphics card functions is used as a switching device of data transmission by use of the mature graphics technology, so that the display interface can transmit data which satisfies the transmission rate requirement to the data transmission device. Moreover, According to the technical scheme, the development difficulty of the data transmission system is reduced, the development period is shortened, and the development cost is reduced.

The invention discloses a LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit, and is used for solving the problem of interface resource waste caused in a way that the LVDS interface and the DSI can not be multiplexed. The circuit comprises a data clock selection circuit, a data clock synchronization circuit, a mode control circuit, a data conversion circuit and a driving circuit, wherein the data clock selection circuit selects a current interface mode, receives a data signal and a clock signal input from outside, and provides the data signal and the clock signal to the data clock synchronization circuit; the data clock synchronization circuit carries out synchronization on the data signal and the clock signal, provided the synchronized data signal and clock signal for the data conversion circuit; the data conversion circuit converts the synchronized data signal to be serial from parallel, and outputs a differential data signal to the driving circuit; and the driving circuit utilizes the differential data signal to control the range of the output signal so as to realize the multiplexing of the LVDS interface and the DSI and reduce resource waste.

A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.

The invention discloses a method for changing a display interface of application software and electronic equipment, wherein the method is applied to an operating system of the electronic equipment; the electronic equipment is provided with a display unit; first application software is at least installed on the operating system; and in addition, the first application software has a first display interface. The method comprises the following steps that: when the current display interface of the display unit displays the first display interface, or the current display interface needs to display the first display interface after a preset time period, whether a changing instruction used for changing the current display interface from the first display interface to a second display interface is obtained or not is detected, wherein the second display interface is different from the first display interface; when the changing instruction is obtained, the second display interface is obtained on the basis of the changing instruction; and the current display interface is controlled to be the second display interface on the basis of first pixel set information corresponding to the first display interface.

The invention provides an NAND (Not And) flash memory which comprises a memory unit, a serial interface, a chip selection enable signal input port, and a control unit, wherein the serial interface comprises a first serial port and a second serial port; the chip selection enable signal input port is used for receiving a chip selection enable signal; and the control unit is used for indicating the first serial port to receive input data when the chip selection enable signal is at a low level, and indicating the second serial port to output the data of the memory unit with a corresponding address after the input data is received. The NAND flash memory can be provided with different interfaces; the application flexibility and the application scope of a chip are improved and extended; the IO (Input / Output) quantity is reduced; and the cost is lowered.

A data processing apparatus has a compressor and an output interface. The compressor generates a compressed display data by compressing a display data according to a compression algorithm. The output interface records indication information in an output bitstream, and outputs the output bitstream via a display interface, wherein the output bitstream is derived from the compressed display data, and the indication information is set in response to the compression algorithm employed by the compressor. Another data processing apparatus has a de-compressor and an input interface. The de-compressor de-compresses a compressed display data derived from an input bitstream. The input interface receives the input bitstream via a display interface, parses indication information included in the input bitstream, and configures the de-compressor to employ a de-compression algorithm as indicated by the indication information.

The application provides an interface conversion method and system. The interface conversion method comprises the following steps: receiving a minimized differential signal of each data channel of a high definition multimedia interface HDMI and a minimized differential signal of a clock channel; converting the minimized differential signal of each data channel of the HDMI and the minimized differential signal of the clock channel to parallel data, so as to obtain the parallel data of each data channel of the HDMI and a HDMI pixel clock; synchronizing the parallel data of each data channel of the HDMI based on the HDMI pixel clock, and decoding the synchronized data; and caching the video data obtained by decoding, and sending the cached video data to a DSI interface based on the video display serial interface DSI protocol. By means of the interface conversion method and system provided by the application, the data of the HDMI interface can be converted to the data that can be output atthe DSI interface; therefore, the conversion of the HDMI interface to the DSI interface is realized.

In an exemplary variable rate display interface, a high-speed reverse data transfer is enabled over plural lanes of a display serial interface (DSI) bus during blanking periods. Further increases in bandwidth of each high-speed reverse data transfer may be achieved by increasing DSI clock speed during the blanking periods. Since a display relies on a host clock to send reverse data, the frequency of the reverse data is increased, which effectively increases the bandwidth of reverse channel lanes. By increasing the reverse bandwidth over existing pins in the DSI bus, more data may be transferred to the host, including raw touch / stylus data rather than processed data. The raw data may then be processed by the host's relatively powerful processors. By shifting the processing to the host, the need for a powerful touch screen controller (TSC) and / or a powerful touch display driver integrated circuit (TDDI) may be avoided.

The invention relates to the technical field of display processing, in particular to a computer readable storage medium and a display stream compression decoding module and display interface interaction device applying the same, a computer program is stored in the medium, and the computer program can be executed by a processor of the display stream compression decoding module and the display interface interaction device. The DSC standard V1.1 specifies that bit stream compression has a fixed compression ratio while the number of slices of a complete image may be 1, 2 or 4. Slice number information is obtained through calculation of a coded and transmitted image parameter set, clock frequencies needed by all the modules are automatically distributed, the input and output time sequence of decoding is controlled, and the method has the advantage of being easy to operate. Data for displaying a serial interface is converted into a DSC bit stream on hardware, and a decoding algorithm in a VESA association DSC standard V1.1 is realized by using the hardware, so that the method is simple and cheap to implement on conventional hardware.

An IP address display device suitable for a power device is provided. The IP address display device comprises a communication interface, a display interface, and a control circuit. The control circuit is electrically coupled to the communication interface and the display interface, and is used to determine whether an IP address allocated by a DHCP server has been obtained through the communication interface. When the determination result is yes, the control circuit automatically displays the obtained IP address by the display interface for a preset time. In addition, a power distribution unit and an uninterruptible power system using the same are also provided.

The invention discloses a method for supporting transparent transmission of serial interfaces. The method comprises the following steps: a first universal asynchronous serial interface of a micro-controller receives real-time communication data of monitored equipment in an interruption receiving manner, and stores the real-time communication data in a first cache array; the newly received data in the first cache array is forwarded to a second universal asynchronous serial interface, and forwarded to communication equipment through the second universal asynchronous serial interface; the second universal asynchronous serial interface of the micro-controller receives the data of the communication equipment in an interruption receiving manner, and stores the data in a second cache array; and the newly received data in the second cache array is forwarded to the first universal asynchronous serial interface, and forwarded to the monitored equipment through the first universal asynchronous serial interface. By means of the method disclosed by the invention, transparent transmission of data can be realized; furthermore, interfaces of the monitored equipment cannot be occupied; and the transmission delay is very low.

The technical scheme of the invention provides a scanning process display method used for magnetic resonance examination. A display interface is divided into a plurality of regions, one region is set as a scanning process display window, when the other regions are switched among different windows, the region fixedly displays the scanning process display window, and therefore a user can see the scanning process display window when the different windows of the system are switched; two display modes are adopted for displaying scanning process related information, the user can know the scanning process of a running protocol in real time and can further check information of already running protocols and not running protocols, and therefore the user can grasp the scanning conditions of all the currently checked protocols on the whole.

The invention provides an electrostatic discharge detection processing method and device and terminal equipment. The method comprises the steps that a display processor triggers a display serial interface DSI to carry out ESD detection; receiving an ESD detection result returned by the DSI; and if the ESD detection result indicates that the screen state is abnormal, the display processor triggers interruption, and ESD recovery is carried out. By utilizing the scheme provided by the invention, ESD detection can be effectively carried out on various different display screens, and the power consumption of the system is not increased.

The invention discloses special equipment for detecting object surface normal errors on the basis of an image reflection method. Image collecting equipment and image display equipment are placed in front of a tested object; an industrial personal computer is connected with the image collecting equipment through wired USB, Gige and Camera link or connected wirelessly, and is connected with the image display equipment through an HDMI (high-definition multimedia interface), a VGA (video graphics array) interface and a DSI (display serial interface); the image collecting equipment is arranged right in front of the tested object, and a lens faces a to-be-tested part and used for collecting shot images of the tested object; the image display equipment is arranged in the position having the same distance with the lower side of the front end of the tested object and the image collecting equipment, and a connecting line of the centers of the image collecting equipment and the tested object and a connecting line of centers of the tested object and the image display equipment are symmetric to a center normal of the tested object.

The invention discloses an on-site portable wireless video debugging tool. The on-site portable wireless video debugging tool comprises a video receiving unit, a video sending unit, and a wireless video transmission module; the video receiving unit and the video sending unit are connected wirelessly; the wireless video transmission module comprises a wireless video sending module and a wireless video receiving module; the video sending unit is composed of a camera video interface, a power interface and a holder control interface all of which are connected with the wireless video sending module; the power interface is connected with an externally connected power source; the holder control interface is connected with an externally connected camera holder; the camera video interface is connected with an externally connected camera; the video receiving unit is composed of a display unit interface, a power supply source and a holder control interface; and the display unit interface and the holder control interface are connected with an externally connected computer. According to the on-site portable wireless video debugging tool, an information bridge between an installer on a tower and a debugging technician under the tower can be established for installation and debugging of a video / image monitoring device at an outdoor transmission tower through a wireless mode. The on-site portable wireless video debugging tool has the advantages of small volume, light weight and carrying convenience.

The present invention provides a smart terminal performance display method and system, wherein the method includes: determining a target terminal and display content according to a user's smart terminal performance display request; the target terminal includes one of the following: a mobile phone, a camera or a tablet computer; The display content includes the appearance and structure of the target terminal, system performance and battery life, as well as the basic functions of each part of the physical hardware of the target terminal and the measured performance corresponding to each basic function; the physical hardware includes: display module, touch module , camera module, and SoC hardware; display the corresponding display interface according to the model of the target terminal and the display content; the display interface includes the target terminal and multiple terminals associated with the model of the target terminal, and the display content of each terminal The various detection items under the display; the performance of the detection items corresponding to the user's current operation instruction is displayed in a graphic and intuitive way. The invention improves the user's subjective initiative and experience in selecting products.

A data processing apparatus has a compressor and an output interface. The compressor performs compression upon an input display data to generate a compressed display data, wherein an error-resilient coding tool is involved in the compression. The output interface packs an output display data derived from the compressed display data into an output bitstream, and outputs the output bitstream via a display interface, wherein the display interface is one of a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) and an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

The invention discloses a LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit, and is used for solving the problem of interface resource waste caused in a way that the LVDS interface and the DSI can not be multiplexed. The circuit comprises a data clock selection circuit, a data clock synchronization circuit, a mode control circuit, a data conversion circuit and a driving circuit, wherein the data clock selection circuit selects a current interface mode, receives a data signal and a clock signal input from outside, and provides the data signal and the clock signal to the data clock synchronization circuit; the data clock synchronization circuit carries out synchronization on the data signal and the clock signal, provided the synchronized data signal and clock signal for the data conversion circuit; the data conversion circuit converts the synchronized data signal to be serial from parallel, and outputs a differential data signal to the driving circuit; and the driving circuit utilizes the differential data signal to control the range of the output signal so as to realize the multiplexing of the LVDS interface and the DSI and reduce resource waste.

The present invention relates to the field of display processing technology, and in particular to a computer-readable storage medium and a display stream compression decoding module and display interface interaction device using the medium. The medium stores a computer program, and the computer program can be displayed by the display stream compression decoding module. Executed by a processor of the device for interacting with the display interface. The DSC standard V1.1 stipulates that bit stream compression has a fixed compression ratio, and the number of slices of a complete image can be 1, 2 or 4. The number of slices is calculated by encoding and transmitting the image parameter set, and then the clock frequency required by each module is automatically allocated, and the input and output timing of decoding is controlled, which is easy to operate. On the hardware, the data of the display serial interface is converted into the bit stream of the DSC, and the decoding algorithm in the DSC standard V1.1 of the VESA Association is implemented by hardware, which makes it simple and cheap to implement on conventional hardware.

The invention discloses a universal data transmission system, comprising a computer host and at least one data transmission device, wherein the computer host is configured with at least one display interface. The computer host is connected with the data transmission device by the display interface. The computer host is mainly used for transmitting high-speed transmitted data to the data transmission device through the display interface according to transmission rate requirements of the data transmission device. The data transmission device receives the data transmitted by the computer host at high speed, and converts the data to be data form required by external equipment which is connected with the data transmission device and outputs the data. In the technical scheme of the invention, a graphics card or an accelerated processing unit having graphics card functions is used as a switching device of data transmission by use of the mature graphics technology, so that the display interface can transmit data which satisfies the transmission rate requirement to the data transmission device. Moreover, According to the technical scheme, the development difficulty of the data transmission system is reduced, the development period is shortened, and the development cost is reduced.