A
clock integration method, tool, and a
computer program product that captures, creates, and seamlessly integrates a
clock specification to achieve a correct-by-
construction design flow of a
semiconductor product, such as an ASIC, from a partially manufactured
semiconductor platform. The clocking elements of the
design flow are combined and displayed to a
chip designer in a plurality of context-driven user interfaces and views. Within each view, the details of the
clock specification are presented in the context of the information to guide a
chip designer to make relevant and correct determinations, e.g., if the context is a high level overview of the logic of the intended
semiconductor product, then only the high level parameters, such as source, frequency, path of the clocks signals through the high level modules, etc. are seen. When a
chip designer wants more or less detailed information, she / he need only
zoom in /
zoom out through the plurality of views of the
design flow. Each view can combine the logical, structural, architectural, cost, timing, and other features of the clock in a particular context. A user can
zoom in all the way to select and manipulate the circuit elements of a PLL, a clock factory element, etc. as in the creation or generation of a clock for the intended semiconductor product. The user can then zoom out and the clock integration method and tool herein determines how changes in selected muxed clock signals and / or elements affect other clocks in the same or other modules and / or the same clock in other modules. Creating, inserting, and integrating clocks for a complex
integrated circuit has never been easier.