37 results about "Cmos power amplifier" patented technology

A power amplifier (PA) provides dynamic stability and gain control for linear and non-linear operation. The PA operates with a baseband processor and a transmitter, in which the PA receives a signal from the transmitter for power amplification prior to transmission of the signal. The PA is configured to select between the linear mode of operation and the non-linear mode of operation, in which device scaling within the PA is achieved by changing a device sizing of at least one stage of the PA. Further to changing the device size, the PA changes biasing resistance and impedance of a matching network in response to the changing of the device size to control power output and stability for the PA.

A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

The invention discloses a 0.1-5GHz ultra-wideband CMOS (complementary metal oxide semiconductor) power amplifier which comprises an input matching circuit, an ultra-wideband driving-stage amplifying circuit, an ultra-wideband power amplifying circuit and an output direct-current blocking circuit. A first ultra-wideband driving stage is used for acquiring preceding-stage gain and guaranteeing ultra-wideband input matching of the integral circuits; an ultra-wideband driving power stage is used for guaranteeing high power output of the integral circuits and an excellent ultra-wide output matching characteristic of the integral circuits. The 0.1-5GHz ultra-wideband CMOS power amplifier has the advantages that a double-stage stacking structure is combined with a compensation capacitive circuit, so that a chip is small in area and wide in bandwidth; parameters of the amplifier can be determined after various indexes such as the gain, bandwidths and output power of the integral circuits are integrated in the integral circuits, so that requirements on high gain, linearity and driving power and flatness at the bandwidth of 0.1-1.5GHz can be met.

The invention discloses a CMOS power amplifier with high linearity. The CMOS power amplifier comprises an amplifier unit and an envelope detection unit. The amplifier unit comprises one or more power transistors used for performing power amplification on input signals to obtain output signals. The envelope detection unit detects the input signals of the power transistors and generates envelope signals to serve as substrate bias voltages of the corresponding power transistors. According to the CMOS power amplifier disclosed by the invention, as the substrate voltages of the power transistors are adjusted by the envelope signals of the input signals of the power transistors, the linearity of the power amplifier can be effectively improved, and compared with the prior art of adjusting the grid voltages or supply voltages of the power transistors by adopting the envelope signals, the linearity is improved more effectively. The CMOS power amplifier further has a certain effect of improving the efficiency of the power amplifier.

Embodiments of the invention may provide CMOS power amplifiers with power mode control to provide the desired power-added efficiency (PAE), idle current, output power, and Adjacent Channel Leakage Ratio (ACLR). For instance, there may be a multi-mode WCDMA CMOS RF power amplifier having high / medium / low output power modes aimed to achieve high PAE and low idle current in a portable wireless environment. According to an example embodiment, a CMOS RF power amplifier may provide a plurality of separate signal paths for purposes of supporting multi-power modes. For example, there may be a first signal path which supports a high-power mode, and a second path which is subsequently divided into two recursive signal paths or sub-paths to support respective medium and low-power modes. One of the three power modes may be selected or controlled using bias control switches in the first and second paths.

CMOS power amplifiers (PAs) are disclosed having one or more integrated one-time programming (OTP) memories that are utilized to control at least in part operation of the CMOS PAs. The integrated OTP memories within the CMOS power amplifiers (PAs) allow adjustments, such as one-time factory trimming, of CMOS PA integrated circuits to optimize or improve performance. With this capability, for example, the tuning and biasing of stages within a multi-stage amplifier within a CMOS PA can be measured during factory test and adjusted by setting one or more bits in the OTP memories, as desired. Further, the operation of other circuitry within the PA can also be controlled at least in part with parameter settings stored in the OTP memories.

The present invention provides a small-sized on-chip complementary metal oxide semiconductor (CMOS) power amplifier with improved efficiency. The on-chip CMOS power amplifier can improve efficiency and maximize its output by increasing the K factor, which can cause problems in power amplifiers with distributed active converter structures. The on-chip CMOS power amplifier, which has improved efficiency and is manufactured in a small size, includes: a primary coil, located in the first layer; a secondary coil, located in the second layer, the second layer being the upper part of the first layer, the secondary coil corresponding Placed at the position of the primary coil; the cross section is used to couple the secondary coils to each other.

There is provided a multi-stage CMOS power amplifier including: a driver amplifier having differential output terminals, inverting differential signals input through first and second input terminals and outputting the respective inverted signals through the differential output terminals; a transformer for power matching having a primary coil connected between the differential output terminals of the driver amplifier and a secondary coil coupled with the primary coil using electromagnetic induction, having a predetermined turns ratio to the primary coil, and connected to a direct current (DC) tuning voltage terminal; and a power amplifier power-amplifying differential signals passing through one end and the other end of the secondary coil of the transformer and outputting the respective power-amplified differential signals through first and second output terminals.

Disclosed is a CMOS power amplifier. A temperature compensation circuit of a CMOS power amplifier may include: a bias circuit unit supplying a gate bias voltage to a power amplification circuit part; a bias detection unit determining a class type of the power amplification circuit part according to the gate bias voltage; a temperature detection unit detecting a temperature-proportional voltage in proportion to ambient temperature; a temperature compensation control unit generating a compensation control value according to the temperature-proportion voltage in the class type determined by the bias detection unit; and a conversion unit converting the compensation control value of the temperature compensation control unit into a linear bias control value and providing the linear bias control value to the bias circuit unit, wherein the bias circuit unit compensates the gate bias voltage according to the linear bias control value of the conversion unit.

An integrated CMOS power amplifier system to improve amplifier performance, the integrated CMOS power amplifier system including a plurality of differential main amplifier cores, a plurality of ground pads, and a plurality of routes to connect the plurality of differential main amplifier cores to the plurality of ground pads. Each differential main amplifier core includes a pair of collocated main amplifier core transistors. Each ground pad is connected to a subset of the differential main amplifier cores. Embodiments of the integrated CMOS power amplifier system decrease parasitic inductance to ground and increase the transconductance and amplification of the integrated CMOS power amplifier system, thus improving performance.

Disclosed herein is a transformer including: a primary coil formed of a first conductor having a predetermined length and including a first end and second end for receiving a signal, wherein the first conductor is formed as a first loop; and a secondary coil that is coupled to the primary coil in an electromagnetic coupling, and is formed of a second conductor having a predetermined length and including a first end and a second end for outputting a signal, wherein the second conductor is formed as a second loop, wherein the primary coil and the secondary coil are stacked while crossing each other. Accordingly, power transformer efficiency may be increased.

A CMOS power amplifier includes: a first MOS transistor connected between a first power terminal and a first output stage and having a gate connected to an input stage; a second MOS transistor connected between the first output stage and a ground and having a gate connected to the input stage; a switching circuit unit connecting or separating a feedback line between the input stage and the first output stage to select a linear amplifying operation or a non-linear amplifying operation; and a resistor formed at the feedback line between the input stage and the first output stage to determine a linear amplification gain when the feedback line is turned on.

Disclosed is a CMOS power amplifier. A temperature compensation circuit of a CMOS power amplifier may include: a bias circuit unit supplying a gate bias voltage to a power amplification circuit part; a bias detection unit determining a class type of the power amplification circuit part according to the gate bias voltage; a temperature detection unit detecting a temperature-proportional voltage in proportion to ambient temperature; a temperature compensation control unit generating a compensation control value according to the temperature-proportion voltage in the class type determined by the bias detection unit; and a conversion unit converting the compensation control value of the temperature compensation control unit into a linear bias control value and providing the linear bias control value to the bias circuit unit, wherein the bias circuit unit compensates the gate bias voltage according to the linear bias control value of the conversion unit.

The invention discloses a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) power amplifier. The CMOS power amplifier comprises an input balun which receives a radio frequency input signal andgenerates a first input signal and a second input signal, a power amplification circuit which performs power amplification on the first input signal to generate a first output signal, and performs power amplification on the second input signal to generate a second output signal, and a power combiner which is connected with the power amplification circuit and generates a radio frequency output signal based on the first output signal and the second output signal. The power amplification circuit comprises a power amplification unit and a bias unit, and the bias unit provides bias current for theoutput end of the power amplification unit so as to eliminate a sub-harmonic component generated during power amplification. According to the CMOS power amplifier, a power synthesis technology is adopted, and the output power of the CMOS power amplifier is greatly improved; and the bias unit for generating the bias current is arranged in the power amplification circuit, so that the linearity of the CMOS power amplifier is greatly improved.

There is provided a complementary metal oxide semiconductor (CMOS) power amplifier including: a load unit connected between an operating voltage supply terminal and an output terminal; an amplifying unit formed as a cascode structure between the load unit and a ground, amplifying a power of an input signal input through an input terminal and outputting the amplified signal through an output terminal; and a threshold voltage control unit varying a threshold voltage of the amplifying unit according to a magnitude of the input signal input through the input terminal.

The invention discloses a CMOS power amplifier matching circuit. The CMOS power amplifier matching circuit comprises a circuit board and an extra-chip matching network and a power amplification integrated chip which are arranged on the circuit board; the power amplification integrated chip comprises a high frequency power amplifier, a low frequency power amplifier and an intra-chip matching network, the high frequency power amplifier is connected with the intra-chip matching network, and the low frequency power amplifier is connected with the extra-chip matching network. The CMOS power amplifier matching circuit can integrate the advantages of the intra-chip matching network and the extra-chip matching network, and a PA is divided into a high frequency part and a low frequency part, wherein the high frequency part is achieved through the intra-chip matching network, and design difficulty of the PCB is decreased; the low frequency part is achieved through the extra-chip matching network, and good performance is achieved.

An integrated CMOS power amplifier system to improve amplifier performance, the integrated CMOS power amplifier system including a plurality of differential main amplifier cores, a plurality of ground pads, and a plurality of routes to connect the plurality of differential main amplifier cores to the plurality of ground pads. Each differential main amplifier core includes a pair of collocated main amplifier core transistors. Each ground pad is connected to a subset of the differential main amplifier cores. Embodiments of the integrated CMOS power amplifier system decrease parasitic inductance to ground and increase the transconductance and amplification of the integrated CMOS power amplifier system, thus improving performance.

The invention discloses a reconfigurable inter-stage matching broadband CMOS power amplifier, and belongs to the technical field of integrated circuits. A received radio frequency input signal is amplified by a driving-stage amplifier and then output to a power-stage amplifier through a reconfigurable inter-stage matching network to be amplified and then output; the reconfigurable inter-stage matching network comprises a CLC matching network, a reconfigurable matching capacitor, a reconfigurable matching inductor and two groups of switches; the two groups of switches are respectively connectedwith the reconfigurable matching capacitor and the reconfigurable matching inductor in series; according to different working frequency bands, the equivalent inductance values of the parallel inductor and the reconfigurable matching device in the CLC network are changed through on-off of the switch, so that the reconfiguration of the matching network is realized. The high-Q-value interstage impedance matching network is simple and reliable in structure, does not influence output power and efficiency, does not increase power consumption, can realize relatively high gain, and can ensure that multiple frequency bands meet high output power and high efficiency, thereby overcoming bandwidth limitation of the high-Q-value interstage impedance matching network and realizing broadband application.

There is provided a multi-stage CMOS power amplifier including: a driver amplifier having differential output terminals, inverting differential signals input through first and second input terminals and outputting the respective inverted signals through the differential output terminals; a transformer for power matching having a primary coil connected between the differential output terminals of the driver amplifier and a secondary coil coupled with the primary coil using electromagnetic induction, having a predetermined turns ratio to the primary coil, and connected to a direct current (DC) tuning voltage terminal; and a power amplifier power-amplifying differential signals passing through one end and the other end of the secondary coil of the transformer and outputting the respective power-amplified differential signals through first and second output terminals.

The invention discloses a CMOS power amplifier chip with an on-chip integrated detection function, and belongs to the technical field of communication. The temperature compensation circuit comprises a power amplifier with the temperature compensation function and a power detector used for detecting the output power of the power amplifier, a resistor is connected to an output port RF_out of the power amplifier in parallel, and a radio frequency signal is transmitted to the input end of a transistor working in a sub-threshold area through the resistor; DC and higher harmonic components are generated through the transistor, and finally, detection voltage Vout is output after RC low-pass filtering, so the amplitude change of the power amplifier can be detected. The CMOS power amplifier chip is simple in circuit structure, small in area, low in cost, excellent in performance and capable of achieving a wide dynamic range and low temperature sensitivity, and a solution is provided for the CMOS power amplifier chip with the silicon-based miniaturized on-chip integrated detection function.

The invention discloses a two-dimensional traveling wave high-gain broadband CMOS power amplifier, which comprises an input power division network, a first input third-order artificial transmission line, a second input third-order artificial transmission line, a drain bias network, a first high-gain two-pile PMOS amplification network, a second high-gain two-pile PMOS amplification network, a third high-gain two-pile PMOS amplification network, a first high-gain two-pile NMOS amplification network, a second high-gain two-pile NMOS amplification network, a third high-gain two-pile NMOS amplification network and an output two-dimensional three-order artificial transmission line network. The core architecture adopts the characteristics of high power and high gain of the high-gain two-pile PMOS and NMOS amplification networks in the microwave band, and meanwhile, the ultra-wideband frequency response characteristic and the simplified series voltage division structure of the two-dimensionaltraveling wave amplifier structure are utilized, so that the whole power amplifier obtains good wideband, high gain, high efficiency and high power output capability, and a power supply network is simple.

CMOS power amplifiers (PAs) are disclosed having one or more integrated one-time programming (OTP) memories that are utilized to control at least in part operation of the CMOS PAs. The integrated OTP memories within the CMOS power amplifiers (PAs) allow adjustments, such as one-time factory trimming, of CMOS PA integrated circuits to optimize or improve performance. With this capability, for example, the tuning and biasing of stages within a multi-stage amplifier within a CMOS PA can be measured during factory test and adjusted by setting one or more bits in the OTP memories, as desired. Further, the operation of other circuitry within the PA can also be controlled at least in part with parameter settings stored in the OTP memories.

The invention belongs to the technical field of millimeter wave communication, and particularly provides a V-band CMOS power amplifier which is used for solving the problems that in the prior art, thecircuit structure is complex, the chip area is large, and the design difficulty of an amplifier matching circuit is large. The amplifier comprises an input matching circuit, a first-stage amplification circuit, an inter-stage matching circuit, a second-stage amplification circuit and an output matching circuit which are connected in sequence, wherein the two stages of amplification circuits are formed by stacking transistors M1 (or M3) and M2 (or M4) respectively; the transistor stacking mode is simple in structure, the breakdown risk of the transistors can be effectively reduced, and the optimal power amplifier saturation output power is obtained; meanwhile, the transistor stacking structure can greatly improve the stability of the millimeter wave power amplification circuit; in addition, the input and output matching circuits in a grounding coplanar waveguide form can further improve the gain and the output power of the millimeter wave amplifier while realizing good input and outputmatching of the stacked transistors in a millimeter wave frequency band.

The invention relates to a radio frequency module integration technology applied to mobile equipment, and discloses an on-chip CMOS power amplifier with a temperature compensation function. The power amplifier comprises a multi-path band-gap reference current source, a first-stage amplifying circuit, a second-stage amplifying circuit, a third-stage amplifying circuit, a first biasing circuit, a second biasing circuit and a third biasing circuit; the multi-channel band-gap reference current source provides current for the three bias circuits, the radio frequency signal input total port is connected with the input end of the first-stage amplification circuit, the output end of the first-stage amplification circuit is connected with the input end of the second-stage amplification circuit, the output end of the second-stage amplification circuit is connected with the input end of the third-stage amplification circuit, and the output end of the third-stage amplification circuit is connected with the radio frequency signal output total port. A three-stage amplification circuit structure is adopted, gain fluctuation and output power fluctuation in high and low temperature states are compensated, and the requirements of a system can be well met.

Disclosed herein is a transformer including: a primary coil formed of a first conductor having a predetermined length and including a first end and second end for receiving a signal, wherein the first conductor is formed as a first loop; and a secondary coil that is coupled to the primary coil in an electromagnetic coupling, and is formed of a second conductor having a predetermined length and including a first end and a second end for outputting a signal, wherein the second conductor is formed as a second loop, wherein the primary coil and the secondary coil are stacked while crossing each other. Accordingly, power transformer efficiency may be increased.

The present invention relates to a micro CMOS power amplifier, in which an output transformer is configured as a substrate of a multilayer structure, and an amplifier circuit module is stacked on the output transformer. The micro CMOS power amplifier includes: an amplifier circuit module chip configured by modularizing circuits for amplifying power as a module; and an output transformer for outputting output of the amplifier circuit module chip to outside through a transformer circuit, in which the output transformer is implemented on a multilayer substrate, and the amplifier circuit module chip and the output transformer are configured as a stack. According to the micro CMOS power amplifier of the present invention described above, an output transformer occupying a large space in a conventional power amplifier is configured as a multilayer substrate, and thus the chip size can be reduced within 50% without decreasing output power of the power amplifier.

The invention discloses an overvoltage protection circuit and an overvoltage protection method of a CMOS power amplifier. The circuit comprises a stack tube circuit, a voltage sensor, a voltage amplitude limiter and a subtracter, one end of the tube stacking circuit is connected with the voltage sensor and the voltage amplitude limiter, and the other end of the tube stacking circuit is connected with the subtracter. According to the circuit, a voltage limiter and a subtracter of a voltage sensor are additionally arranged on the basis of an original stack tube circuit; the two MOS tubes in thestacked tube circuit are protected against breakdown under the limit working condition, the voltage of the whole CMOS power amplifier circuit under the limit condition can be adjusted to be within thesafety range according to the negative feedback adjustment principle, and the circuit is simple and reasonable in design, safe and reliable. Meanwhile, the method can improve the safety and reliability of the CMOS power amplifier, and guarantees that the CMOS power amplifier can still work safely under the overvoltage condition.

The embodiment of the invention provides a CMOS (Complementary Metal Oxide Semiconductor) power amplifier and electronic equipment. The CMOS power amplifier comprises a first CMOS tube, a second CMOS tube and a feedback adjustment circuit; the grid electrode of the first CMOS tube is connected with the input end of the CMOS power amplifier, the drain electrode of the first CMOS tube is connected with the source electrode of the second CMOS tube, the drain electrode of the second CMOS tube is connected with the output end of the CMOS power amplifier, the first end of the feedback adjustment circuit is connected with the output end of the CMOS power amplifier, and the second end of the feedback adjustment circuit is connected with the grid electrode of the second CMOS tube; when the voltage of the output end of the CMOS power amplifier is greater than the break-over voltage corresponding to the feedback adjustment circuit, the feedback adjustment circuit is conducted, so that the problem that the CMOS power amplifier is broken down by over-high peak voltage to be damaged can be prevented under the condition of oscillation or load mismatch, and the reliability of the CMOS power amplifier is improved.