35 results about "Cache compression" patented technology

Data in a cache is selectively compressed based on predictions as to whether the benefit of compression in reducing cache misses exceeds the cost of decompressing the compressed data. The prediction is based on an assessment of actual costs and benefits for previous instruction cycles of the same program providing dynamic and concurrent adjustment of compression to maximize the benefits of compression in a variety of applications.

A data processing apparatus 1 comprises data processing circuitry 2, a memory 8 for storing data and a cache memory 5 for storing cached data from the memory 8. The cache memory 5 is partitioned into cache segments 12 which may be individually placed in a power saving state by power supply circuitry 15 under control of power control circuitry 22. The number of segments which are active at any time may be dynamically adjusted in dependence upon operating requirements of the processor 2. An eviction selection mechanism 35 is provided to select evictable cached data for eviction from the cache. A cache compacting mechanism 40 is provided to evict evictable cached data from the cache and to store non-evictable cached data in fewer cache segments than were used to store the cached data prior to eviction of the evictable cached data. Compacting the cache enables at least one cache segment that, following eviction of the evictable cached data, is no longer required to store cached data to be placed in the power saving state by the power supply circuitry.

Data in a cache is selectively compressed based on predictions as to whether the benefit of compression in reducing cache misses exceeds the cost of decompressing the compressed data. The prediction is based on an assessment of actual costs and benefits for previous instruction cycles of the same program providing dynamic and concurrent adjustment of compression to maximize the benefits of compression in a variety of applications.

The invention discloses a multilevel cache based on an SSD RAID array and a caching method and belongs to the field of solid state disk storage technology. The multilevel cache is designed, wherein anupper-layer cache is realized through a small-capacity NVRAM and is responsible for compressing data, backing up the data to a DRAM, integrating the compressed data and metadata of the compressed data into a page for storage and scheduling the data to a lower-layer cache with stripes being units; and the lower-layer cache is realized by separating a part of space from an RAID and is responsible for caching the compressed data, maintaining a mapping table of the original data and the compressed data, restoring the compressed data to the RAID and performing power-fail recovery on the mapping table. The multilevel caching method based on the SSD RAID array is also implemented. Through the technical scheme, according to the characteristic that redundancy between new data and old data is large, the compressed data is managed and stored in the multilevel cache, the demand for cache capacity is reduced, and the cost and the error rate are lowered; and multilevel cache design ensures system reliability, and regardless of the DRAM, the NVRAM or the RAID, timely recovery can be realized in case of data loss or errors.

The invention provides a Cache compression method and device. The method comprises the steps that a to-be-compressed Cache block is acquired; at least two compression algorithms are adopted to compress the to-be-compressed Cache block, compression results of all the compression algorithms are generated, and compression rates of all the compression algorithms are determined according to the compression results of all the compression algorithms; the optimal compression rate is determined according to the compression rates of all the compression algorithms, and the compression algorithm corresponding to the optimal compression rate is determined; and the compression result of the compression algorithm corresponding to the optimal compression rate is written into a write-back cache region. The compression algorithms are combined, the compression rates and the compression results of the compression algorithms are arbitrated, the compression rates and a decompression delay are balanced, and the compression method with a high compression rate and a short decompression delay is provided.