119 results about "10 Gigabit Ethernet" patented technology

An Ethernet mapping enables high speed Ethernet data streams having a data rate of 10 Gb / s to be transported across a synchronous packet switched network fabric having a standard SONET OC-192 line rate of 9.953280 Gbaud. The 10 Gb / s Ethernet data stream is compressed by removing interframe gaps between successive MAC frames to produce a compressed data stream, which is then mapped to a synchronous container. The synchronous container is then launched across the synchronous packet switched network fabric at a standard SONET OC-192 line rate of 9.953280 Gbaud. The synchronous container is preferably provided as a stripped STS-192c frame having only A1 and A2 octets of the Transport Overhead (TOH). The compressed data stream is mapped directly to the synchronous container, starting at the first octet following the A1 and A2 octets, without first being inserted into a conventional STS-192c SPE, so that most of the space normally used for TOH and Path overhead (POH) within a conventional STS-192c frame is freed-up for carrying the compressed data stream. At a receiving interface, the compressed data stream is extracted from received synchronous containers and decompressed, by insertion of interframe gaps between successive MAC frames, to generate a recovered 10 Gb / s Ethernet data stream. The starting bit of each successive MAC frame can be identified by examination of the length field of the immediately previous MAC frame.

A networking / communication chip having a receiving buffer or FIFO whereby it receives data from a data source across a network and transfers the data to a host system. The memory in the host system acts as a logical extension of the receiving buffer in the chip; in this way, the host system controls the flow of data from the source, rather than the control flow being based on the capacity of the receiving buffer in the networking / communication chip. The networking / communication chip may be a controller, such as a 10 Gigabit Ethernet controller, wherein data received from the source in one protocol is transformed to a second protocol input to the host. If either or both the networking / communication chip or the host system is / are made of FPGAs, it / they can be reprogrammed to disable the flow control in the networking / communication chip and enable flow control in the host system. Data flow is enhanced because memory in the host system typically is much larger than memory in the networking / communication chip.

Provided are an apparatus for multiplexing Gigabit Ethernet frames and an apparatus for demultiplexing 10-Gigabit Ethernet frames. The apparatus for multiplexing Gigabit Ethernet frames includes at least one pre-processing unit, a multiplexing unit, an SDR / DDR conversion unit, and a control unit. The at least one pre-processing unit receives Gigabit Ethernet frames, converts the Gigabit Ethernet frames into 10-Gigabit Ethernet frames, and outputs the 10-Gigabit Ethernet frames. The multiplexing unit receives the 10-Gigabit Ethernet frames, time division multiplexes the 10-Gigabit Ethernet frames in frame units, and outputs the time division multiplexed 10-Gigabit Ethernet frames as first data. The SDR / DDR conversion unit, which converts the first data into second data having two 32-bit bus structures and outputs the second data. The control unit outputs a first control signal in response to an output request of the pre-processing unit.

The present invention discloses a method of mapping Optical Payload Unit (OPU) k (k=1, 2, 3 or any positive integer) Ethernet signals (E) into Optical Transport Network (OTN) frames for 10 Gigabit Ethernet (10 GbE) Local Area Network Physical Layer (LAN PHY), wherein OPUk Overhead (OH) is altered by the relocation of Justification Control (JC) bytes, from the standardized ITU-T G.709 locations, into the novel locations of rows 1-3 of column 15. This allows for rows 1-4 of column 16 to be available for any type of Justification Overhead (JOH), such as four Negative Justification Opportunity (NJO) byte locations. Four NJO byte locations, combined with four Positive Justification Opportunity (PJO) byte locations in rows 1-4 of column 17, provides for up to nine justification state choices to be determined by the JC bytes. In addition, the ability to add or remove a plurality of two, three or fours bytes from OTN Payload can double, triple, or quadruple the standardized maximum bit rate tolerance of ±65 parts per million (ppm).

The invention discloses a method and a system for monitoring high-performance IP (Internet Protocol) media stream. The method comprises the following steps of: for the media streams on a high-load Ethernet link, according to an IP key field, allocating different media streams to a plurality of CPUs (Central Processing Units) by a Hash algorithm to perform multi-thread KPI (Key Performance Indicator) statistics; and then, combining the KPI data generated by each CPU, thereby forming the KPI statistic result of all the media streams on the whole link. The method and the system can execute real-time VoIP (Voice over Internet Protocol) and IPTV (Internet Protocol Television) media stream quality of service (QoS) and quality of experience (QoE) parameter statistics on a Gigabit / 10 Gigabit Ethernet interface, thereby reducing the cost of the monitoring system.