32results about How to "Suppress voltage changes" patented technology

An electro-optical device includes red, green, and blue sub pixels and red, green, and blue data lines connected to the corresponding sub pixels. Red, green, and blue sampling switches are provided in a peripheral region and are electrically connected to data lines of the corresponding color. The green sampling switch is located at a position that is closer to the pixel region than are the red or blue sampling switches.

A charging device including an assembled battery having plural secondary batteries serially connected, a charge power source unit which supplies charging current to both ends of said assembled battery having plural secondary batteries serially connected, and plural charge controllers which connect to both ends of each secondary battery among said plural secondary batteries; wherein said charge power source unit includes a charging current output unit which outputs charging current to said assembled battery, and a control unit which controls the current of said charging current output unit based on notification of the bypass current from said charge controllers; and wherein each of said plural charge controllers includes a current control unit which bypasses the current that flows to said secondary battery when the terminal voltage of said secondary battery has reached a preset voltage value, and a notification unit which notifies the control unit of said charge power source unit of said bypass current.

The invention relates to power systems and automation, in particular to a system and a method for improving FRT (fault ride-though) capability of a DFIG-WT (doubly fed induction generator based wind turbine) on the basis of an SFCL (superconducting fault current limiter) and an SMES (superconducting magnetic energy storage). The system is characterized in the on the basis of the typical DFIG-WT, aresistor type SFCL is mounted on the stator side of the DFIG-WT, and the SMES is mounted on a direct current link of the DFIG-WT through a bidirectional DC / DC converter; the resistor type SFCL is used for limiting stator fault current of the DFIG-WT, improving generator terminal voltage sag of the DFIG-WT and absorbing partial surplus active power in the DFIG-WT; the SMES is used for stabilizingunbalanced power and electromagnetic torque oscillation. According to an FRT method for the DFIG-WT on the basis of the SFCL and the SMES, fault current can be limited under symmetrical faults and asymmetrical faults, voltage change is inhibited, and unbalanced power and electromagnetic torque oscillation are stabilized. Efficient FRT support can be provided for the DFIG-WT during FRT, and transient performance of the DFIG-WT is improved.

A data processing device including a power supply terminal having a first power supply voltage applied thereto; a regulator that generates a second power supply voltage based on the first power supply voltage; an internal circuit having an operation clock, wherein the second power supply voltage is supplied to the internal circuit through a power supply; and a power supply voltage variation suppressor connected between the power supply terminal and the power supply line. In this device, the power supply voltage variation suppressor sets an auxiliary period and supplies auxiliary current to the power supply line during the auxiliary period, and wherein the auxiliary period is synchronized with the operation clock of the internal circuit.

An image display apparatus and method that provides a flicker-proof thin-film-transistor liquid-crystal-display (TFT-LCD) is provided. The TFT-LCD has a first pixel circuit group having a plurality of first pixel circuits each having a first capacitance; a second pixel circuit group having a plurality of second pixel circuits each having a second capacitance; and a third pixel circuit group having a plurality of the first pixel circuits and the second pixel circuits arranged in accordance with a weighted average of m number of first pixel circuits and n number of second pixel circuits. The m and n first and second pixel circuits form an average third capacitance greater than the first capacitance of the plurality of first pixel circuits but less than the second capacitance of the plurality of second pixel circuits, wherein m and n are positive integers. The pixel circuit groups are formed on a matrix substrate.

A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.

The present disclosure describes a driver circuit, a light-emitting display device, and a driving method. Even in the case that other video control driving, e.g., fake data insertion driving, is performed during sensing driving, the sensing is not influenced by the other video control driving, e.g., fake data insertion driving. Sensing errors are prevented, and image quality is improved.

A discharge circuit for discharging a capacitor disposed in a power conversion circuit. The discharge circuit includes: a conduction path connecting the power conversion circuit and input terminals; plural resistors disposed in the conduction path, dividing voltage difference between voltage at the input terminal and reference voltage; a connection path connecting a pair of conduction paths; a switch disposed in the connection path, which opens and closes the connection path, the switch being controlled electrically; and a control unit that controls the switch to be opened or closed, the control unit controls the switch to be closed in order to make a closed loop circuit including the capacitor and the connection path. The connection path is disposed between the pair of conduction paths to include at least one resistor of the plurality of resistors in the closed loop circuit when the switch is closed by the control unit.

Display device wherein change of the amount of light of the light-emitting elements caused by change of the number of light-emitting elements that emit light simultaneously is small. This display device includes a display panel having light-emitting elements arranged in matrix fashion; data lines for applying anode potential to light-emitting elements of the same column; scanning lines for applying cathode potential to light-emitting elements of the same row; and a control circuit that adjusts voltage between the anode and cathode of the light-emitting elements based on the number of light-emitting elements that emit light simultaneously. The control circuit suppresses changes of voltage between the anode and cathode of the light-emitting elements caused by a change in the number of light-emitting elements that emit light simultaneously. Accordingly, change of the amount of light of the light-emitting elements is suppressed.

A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input / output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.

In an arrangement with four PDs (PD1 to PD4) aligned along the column direction sharing the signal voltage reading unit, respective elements are disposed in the order of: PD / FD1 and TG-Tr1,2 / PD2 / SF-Tr and SL-Tr / PD3 / FD2 and TG-Tr3, 4 / PD4 / RS-Tr.

A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

An optical print head includes: light-emitting elements in line shape; first power line supplying first reference voltage; second power line supplying drive current to each light-emitting element and supplying second reference voltage; DAC outputting first voltage indicating light emission amount of each light-emitting element; first elements for holding first voltage difference between the first reference voltage and the first voltage; second elements each electrically connectable with corresponding first element and for holding second voltage difference between the second reference voltage and second voltage according to the first voltage, and during supply of drive current, controls each first element to hold the first difference by electrically disconnecting the first and second elements, and temporarily suspends supply of the drive current, and controls the second element to hold the second difference by electrically connecting the first and second elements, such that the drive current according to the second voltage difference is supplied.

An electro-optical device includes a first scanning line to which a first signal is supplied, a second scanning line to which a second signal is supplied, the second signal being an inverted signal of the first signal, a data line, a first capacitor having a first end and a second end, a first transistor that is controlled in accordance with the first signal, the first transistor electrically interposed between the data line and the first end of the first capacitor, a second capacitor electrically interposed between the second scanning line and the first end of the first capacitor, an electro-optical element that is controlled in accordance with an electric potential held by the first capacitor.

A lateral electric field type liquid crystal display apparatus includes a first substrate on which pixels are disposed in a matrix shape, each of the pixels including a plurality of signal wirings and a plurality of scanning wirings which intersect each other, a switching element provided in a region adjacent to a portion in which the signal wiring and the scanning wiring intersect or on the scanning wiring, a pixel electrode connected to the switching element, and a counter electrode to which a common potential is supplied from a common potential wiringa second substrate provided to face the first substrateand a liquid crystal provided between the first and second substrates, wherein a first electric field shield electrode, which is set to the common potential, is provided between the signal wiring and the first substrate, and the first electric field shield electrode is electrically connected with a first wiring which supplies the common potential to the first electric field shield electrode, within a display region, and an electric field substantially parallel to the first substrate is applied between the pixel electrode and the counter electrode.

A display device includes a plurality of gate lines, a plurality of data lines, a gate circuit, a driver, and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel. The data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines. Each of the time division switches and the timing adjustment switches is an NMOS transistor. The driver turns on the timing adjustment switches connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches connected to the data lines to which negative output signals are output from the driver, by a predetermined period.

An electro-optical device includes red, green, and blue sub pixels and red, green, and blue data lines connected to the corresponding sub pixels. Red, green, and blue sampling switches are provided in a peripheral region and are electrically connected to data lines of the corresponding color. The green sampling switch is located at a position that is closer to the pixel region than are the red or blue sampling switches.

Differential voltage generators receive an initial target voltage, and provide the initial target voltage to a first offset element and a second offset element. The first offset element includes first transistors, and the second offset element includes second transistors. Each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage. The second transistors are capable of removing a current generated by the first transistors, thereby causing an opposite current and leaving the initial target voltage unaffected on a second output. Each of the first transistors has a corresponding second transistor that produces the same current. A first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage.

The present disclosure relates to a voltage driving pixel circuit, a display panel and a driving method thereof. The voltage driving pixel circuit comprises: any two power lines and a load connected in each power line, wherein there is one or more switching circuits between the any two power lines. By means of the voltage driving pixel circuit of the present disclosure, the power lines form a network structure in the light emitting phase, so as to avoid voltage change of the power line voltage Vdd of each row in the pixel in the light emitting phase, thereby improving lateral resistance drop and crosstalk phenomenon of the variable power line voltage Vdd.

There is provided a piezoelectric actuator including: a plurality of piezoelectric elements forming first and second piezoelectric element rows, and including first, second electrodes and piezoelectric portion; an electrode conductive portion; a contact section; a plurality of drive wires,; and conductive wires. A part of the drive wires corresponding to the piezoelectric elements of the second piezoelectric element row are extended toward the contact section while passing between two adjacent piezoelectric elements of the first piezoelectric element row which are adjacent in the first direction. The conductive wires are arranged between two adjacent piezoelectric elements of the second piezoelectric element row, each of the conductive wires is conducted, at two locations thereof apart in the second direction, with the electrode conductive portion.

There is provided a piezoelectric actuator including: a plurality of piezoelectric elements forming first and second piezoelectric element rows, and including first, second electrodes and piezoelectric portion; an electrode conductive portion; a contact section; a plurality of drive wires; and conductive wires. A part of the drive wires corresponding to the piezoelectric elements of the second piezoelectric element row are extended toward the contact section while passing between two adjacent piezoelectric elements of the first piezoelectric element row which are adjacent in the first direction. The conductive wires are arranged between two adjacent piezoelectric elements of the second piezoelectric element row, each of the conductive wires is conducted, at two locations thereof apart in the second direction, with the electrode conductive portion.

An uninterruptible power supply circuit is provided. The uninterruptible power supply circuit includes a first diode, a second diode, a bridge rectifier, and one or more electrical loads. The first diode, the second diode, the bridge rectifier, and the one or more electrical loads are electrically connected in the uninterruptible power supply circuit to drive the one or more electrical loads with a DC voltage or the intended AC supply voltage when the AC supply voltage is cutoff.

A display device includes a plurality of gate lines, a plurality of data lines, a gate circuit, a driver, and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel. The data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines. Each of the time division switches and the timing adjustment switches is an NMOS transistor. The driver turns on the timing adjustment switches connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches connected to the data lines to which negative output signals are output from the driver, by a predetermined period.

An optical print head includes: light-emitting elements in line shape; first power line supplying first reference voltage; second power line supplying drive current to each light-emitting element and supplying second reference voltage; DAC outputting first voltage indicating light emission amount of each light-emitting element; first elements for holding first voltage difference between the first reference voltage and the first voltage; second elements each electrically connectable with corresponding first element and for holding second voltage difference between the second reference voltage and second voltage according to the first voltage, and during supply of drive current, controls each first element to hold the first difference by electrically disconnecting the first and second elements, and temporarily suspends supply of the drive current, and controls the second element to hold the second difference by electrically connecting the first and second elements, such that the drive current according to the second voltage difference is supplied.

A data processing device including a power supply terminal having a first power supply voltage applied thereto; a regulator that generates a second power supply voltage based on the first power supply voltage; an internal circuit having an operation clock, wherein the second power supply voltage is supplied to the internal circuit through a power supply; and a power supply voltage variation suppressor connected between the power supply terminal and the power supply line. In this device, the power supply voltage variation suppressor sets an auxiliary period and supplies auxiliary current to the power supply line during the auxiliary period, and wherein the auxiliary period is synchronized with the operation clock of the internal circuit.

A power conversion device suppresses voltage variation of a power supply bus. The device includes a variation compensation circuit and a control circuit. The variation compensation circuit includes: a first capacitor connected to the power supply bus; a second capacitor connected in series between the first capacitor and a ground; an auxiliary capacitor; and a converter including a switching element and having a voltage step-down function, the converter being connected to the second capacitor and the auxiliary capacitor. The control circuit includes a proportional resonant control section having a peak gain for variation with a frequency ω0 which is twice a frequency of the single-phase alternating current. The control circuit uses the proportional resonant control section to generate a signal for controlling the switching element.

A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.

A memory device according to an embodiment of the present technology includes: a plurality of memory cells arranged in a matrix; a plurality of row wirings connected to one end of each memory cell; a plurality of column wirings connected to the other end of each memory cell; A first decoder circuit connected to each row wiring of the even-numbered rows; a second decoder circuit connected to each of the row wirings of the odd-numbered rows; a third decoder circuit connected to each of the column wirings of the even-numbered columns; and Quad decoder circuit, connected to each column wire of odd columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are composed of mutually independent circuits.