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181 results about "Computer design" patented technology

Self-optimization with interactions

A method for computer-generating interaction-specific knowledge base for rapidly improving or optimizing a performance of an object comprises performing, according to computer-designed test matrices, at least several automatic experimental cycles on selected control variables. In at least one of the automatic experimental cycles after the first the computer plans a new test matrix designed to minimize or remove at least one expected two-variable interaction from a main effect of a designated control variable. A machine operating according to the method is also available.
Owner:LI FAMILY HLDG

Comprehensive management system for platform and load integrated satellite

The invention provides a comprehensive management system for a platform and load integrated satellite and relates to the technical field of aerospace aviation. The problems that the resource use rate is low and extendibility can not be achieved due to the fact that a distributed type satellite-borne computer design method is adopted in an existing satellite electronic system are solved. The comprehensive management system for the platform and load integrated satellite comprises an integrated comprehensive control unit and a standard function extension unit. The standard function extension unit is interconnected with the integrated comprehensive control unit through an external CAN bus. The integrated comprehensive control unit is composed of a comprehensive management module, a communication interface module, a secondary power source and an arbitration logic control module. The standard function extension unit comprises an order control panel, an active temperature control panel and a mechanism control panel. According to the comprehensive management system, resources are integrated, the number of single machines and elements is reduced, orders are integrated, the order types and forwarding links are reduced, telemetering is integrated, redundant telemetering is reduced so that the bandwidth can be increased, functions are integrated, test links and test procedures are reduced, performance is integrated, and the size, the weight and power consumption of equipment are reduced.
Owner:CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI

Computer design method of standard distribution network line

The invention discloses a computer design method of a standard distribution network line. The computer design method of the standard distribution network line comprises the steps of drawing construction diagrams of overhead power distribution lines and cable lines according to distribution line design requirements and a standard diagram, accurately counting materials required by a project, and automatically generating various kinds of report forms. According to the computer design method of the standard distribution network line, the ERP (Enterprise Resource Planning) material entering process can be greatly optimized, and moreover, a preliminary budget of the material part can be automatically embedded into a rural network project preliminary budget template, and the differences between the construction diagram and an as-constructed diagram are analyzed to generate a material balance sheet after the construction diagram and the as-constructed diagram are accomplished, so that a data support is provided for the material recovery, the project auditing and the construction cost, the project materials can be managed and controlled, and create favorable conditions are created for the fixed-assets management, the base data management and the distribution network operation and maintenance management of the post-stage project.
Owner:XUYI POWER SUPPLY OF JIANGSU ELECTRIC POWER +2

Double-faced jacquard weaving technology

ActiveCN105420911AThe pattern is distinctNice appearanceWarp knittingYarnSurface layer
The invention provides a double-faced jacquard weaving technology. A double-needle spaced fabric adopts computer-designed jacquard patterns and is woven by adopting seven guide bars, and the guide bar GB1, the guide bar GB2, the jacquard guide bar JB3.1, the jacquard guide bar JB3.2, the jacquard guide bar JB4.1, the jacquard guide bar JB4.2 and the guide bar GB5 are sequentially arranged from a front needle bed to a back needle bed. The double-faced jacquard weaving technology specifically comprises the following steps that 1, the guide bar GB1 is fully threaded to serve as a first layer of yarn to be laid to form loops on the front needle bed and used for forming the surface layer of the double-needle spaced fabric; 2, the guide bar GB2 is fully threaded to serve as a second layer of yarn to be alternated to form loops to form spaced yarn for connecting the surface layer with the bottom layer; 3, the guide bar GB5 is fully threaded to serve as a fifth layer of yarn to be laid to form loops on the back needle bed and used for forming the bottom layer of the double-needle spaced fabric. The double-needle spaced fabric made through the double-faced jacquard weaving technology is clear in pattern hierarchy and has the good stereoscopic effect in visual sense; meanwhile, the production procedures are simplified, and the cost is greatly saved.
Owner:SINCETECH FUJIAN TECH CO LTD

Microprocessor with integrated high speed memory

The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load / store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load / store unit contains a high speed memory directly interfacing said load / store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load / store data transactions per cycle. By including a high speed memory inside the load / store unit, the processor is directly interfaced from its load / store units to the caches and efficiency gains are achieved by reusing the data information already present in the high speed memory structure of the load / store unit.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE

Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations

The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load / store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load / store unit contains a high speed memory directly interfacing said load / store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load / store data transactions per cycle. By including a high speed memory inside the load / store unit, the processor is directly interfaced from its load / store units to the caches and efficiency gains are achieved by reusing the data information already present in the high speed memory structure of the load / store unit.
Owner:AVAGO TECH WIRELESS IP SINGAPORE PTE

Amalgamation of data models across multiple applications

A method, apparatus, and article of manufacture provide the ability to synchronize project data models across multiple computer applications. A first computer design application in a first client computer obtains files that provide a first application project definition specific to the first computer design application. A first application specific conversion application converts, on the first client computer, the first application project definition into a unified project definition that is utilized by a server application. The unified project definition is transmitted to the server application that stores the definition and synchronizes it with additional computer design applications.
Owner:AUTODESK INC

Preparation method of zirconium dioxide false tooth

InactiveCN102579147AImproving the cosmetic restoration of teethQuality improvementDental prostheticsNumerical controlDentures
The invention relates to the field of false teeth and in particular relates to a preparation method of a zirconium dioxide false tooth. The preparation method comprises the following steps: scanning a tooth model via a three-dimensional scanner, transmitting data to a computer, designing through the computer, further transmitting the well designed data to a five-axis numerical control machine tool, completing tooth processing treatment through the five-axis numerical control machine tool, taking out a product, then performing dyeing, and further placing into a sintering furnace for sintering. Compared with the prior art, according to the preparation method disclosed by the invention, a manual false tooth manufacturing process is fundamentally changed, and traditional waxing, casting, porcelain coating and porcelain turning are replaced by computer design and digital processing; and the process steps are simplified, the digital processing precision is improved, a zirconium dioxide all porcelain crown which can not completed by the manual process can be realized, and the tooth esthetical restoration means of a clinician and the quality of the false tooth can be improved.
Owner:深圳市金悠然科技有限公司

Data storage structure and data access method for multiple core processing system

The invention relates to the technical field of computers, aims to solve the problem that according to a multiple core processor, the data storage delay is large, the transmitting efficiency is low, and the multiple core calculating unit array parallel calculating efficiency cannot be improved continuously and provides a data storage structure for the multiple core processing system and a data access method for the data storage structure of the multiple core processor. The accessing and storing costs of the multiple core processing system can be reduced, and the accessing and storing efficiency is improved, and the parallel calculating efficiency of the multiple core processor can be improved. Thus, according to the technical scheme, the data storage structure for the multiple core processing system comprises a global shared memory, a foreign data transmission controller and an internal data transmission controller. The data storage structure and the data access method for the multiple core processing system are mainly applied to computer design and manufacture.
Owner:TIANJIN SAIXIANG TECH

Parallel computation and distribution control method for flight simulation system

The invention discloses a parallel computation and distribution control method for a flight simulation system. The flight simulation system comprises a main control node, a simulation computation node, an instrument display node, an instructor console node, a visual system node, a motion system node, an operation loading system node and an interface node; by means of reflective memory real-time network accessing, the simulation computation node, the instrument display node and the visual system node form a two-level network through a gigabit Ethernet; by means of parallel computation, the computations of the simulation system, instructor console system, multi-channel visual system, operation loading system and motion system are implemented, computers executing different tasks are scheduled comprehensively through the distribution control technology, and the uniformed scheduling of the systems are implemented through synchronous clock computation and data information sharing. The entire computer cost is reduced, the entire computer design risks are reduced, and an important role is played for improving the scalability and fault processing capability of the system.
Owner:冯岩

Microprocessor with integrated high speed memory

The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load / store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load / store unit contains a high speed memory directly interfacing said load / store unit to the cache. The present invention improves the of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load / store data transactions per cycle. By including a cache memory inside the load / store unit, the processor is directly interfaced from its load / store units to the caches. Thus, the present invention accelerates data accesses and transactions from and to the load / store units of the processor and the data cache memory.
Owner:AVAGO TECH INT SALES PTE LTD
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