66 results about "Bias stress" patented technology

The invention discloses a pixel circuit, a driving method of the pixel circuit, an organic light-emitting display panel and a display device. A unified public voltage signal is inputted to a first electrode of a drive transistor before a data signal is written into a control electrode of the drive transistor; the public voltage signal and a threshold voltage of the drive transistor are written into a control electrode of the drive transistor, so that relatively high current can pass through the drive transistor, threshold voltage deviation, which is caused by bias stress, of the drive transistor can be recovered, a retarding effect of the drive transistor can be improved and the occurrence of a ghosting phenomenon can be prevented; in addition, when the data signal is written into the control electrode of the drive transistor, a time of writing the data signal can be shortened, and the control electrode and the first electrode of the drive transistor can achieve jump through a unified potential, so that a difference, which is caused by stray capacitance between the control electrode and the first electrode of the drive transistor, can be prevented, the problem that threshold voltage grabbing is inconsistent due to voltage jump can be avoided and consistent brightness of the first frame after high-low grayscale switching can be guaranteed.

Disclosed is a shift register capable of mitigating gate bias stress. The shift register, including a plurality of stages, includes an output buffer having a pull-up transistor and two pull-down transistors, each with gates connected to different nodes. One of the two pull-down transistors operates during an even frame portion of an LCD operation; and the other of the two pull-down transistors operates during an odd frame portion of the LCD display operation. Alternating operation of the pull-down transistors substantially mitigates gate stress, and substantially enables the shift register to be fabricated with amorphous silicon.

The invention discloses electronic devices with low refresh rate display pixels. The display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controllingeach pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

A shift register and an LCD device to prevent the deterioration of a transistor by controlling a bias stress are disclosed. The shift register includes a plurality of stages for sequential shift signals, wherein each of the plurality of stages is connected with first and second supplying voltage input lines having opposite phases inversed by at least every frame, a start pulse input line, and at least one clock signal input line in which a phase of a first logic state is shifted in sequence, and a clock signal inputted to the clock signal input line is maintained in a second logic state different from the first logic state during a blanking time between frames.

A shift register for use with a liquid crystal display device includes a plurality of stages. A stage of the shift register includes a first controller, a second controller and an output buffer. The first controller charges and discharges a first node. The second controller charges and discharges a second node and a third node. The output buffer outputs a first output signal in response to the state of the first node and a second output signal in response to the state of the second and third nodes. The shift register may be adaptive to avoid a malfunction caused by a gate bias stress.

A method of detecting thin film transistor (TFT) defects in a TFT-liquid crystal display (LCD) panel, includes, in part, applying a stress bias to the TFTs disposed on the panel; and detecting a change in electrical characteristics of the TFTs. The change in the electrical characteristics of the TFTs may be detected using a voltage imaging optical system or an electron beam. The panel temperature may be varied while the bias stress is being applied. The change in the electrical characteristics is optionally detected across an array of the TFTs.

A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

The invention relates to an electronic display with a hybrid in-pixel and external compensation. A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixelthreshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh ratedisplays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.