A
system and method for reducing impedance loading of
semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I / O pad connection. The method comprises providing a fuse device between the I / O pad connection and the protective device; connecting a
current source device associated with each fuse device in the
integrated circuit, the
current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the
current source and the I / O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I / O connection. Such a
system and method is employed in a memory
system comprising
integrated circuit chips disposed in a stacked relation, with each
chip including: a layer of active circuitry formed at a first layer of each
chip; a plurality of through conducting structures disposed substantially vertically through each
chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing
data access latency in
memory systems employing memory chips such as
DRAM.