47results about How to "Execution does not affect" patented technology

The present invention provides a method and device for executing a single-chip program. The method includes: when starting the operation of the single-chip microcomputer, starting a timer in the single-chip microcomputer to time the target time of the delay program included in the single-chip microcomputer, wherein the delay The program is a program that is set to delay the operation of the above-mentioned target time; when the timing time reaches the target time, the identification information corresponding to the delay program stored in the timer is converted from the first identification to the second identification; In the case of the delay program, it is detected whether the identification information stored in the timer is the second identification; if it is detected that the identification information is the second identification, the delay program is executed. The invention solves the problem of low execution efficiency of the single-chip computer program in the related art, and further achieves the effect of improving the execution efficiency of the single-chip computer program.

The invention is applicable to the technical field of solid state storage, and provides a flash memory controller and a control method thereof as well as flash memory storage equipment. The control method of the flash memory controller comprises the following steps: a command generating state machine receives commands from a plurality of command interfaces of the flash memory, translates the commands and then transmits to a core controller, and pre-writes the address of commands completion state information into a buffer register; the core controller executes the commands and a data address state machine provides the data address for the core controller according to the execution dynamic of the core controller; and after the core controller executes the commands, a command recovering state machine inquires the commands completion state information corresponding to the commands from the core controller, and writes the command completion state information into an internal memory according to the address of the buffer register. Therefore, the execution speed of the commands can be increased; the core controller has sufficient commands to realize high-performance data transmission; the performance of the flash memory controller is guaranteed; and the generating and recovering efficiency of the commands is improved.

The invention relates to a method for realizing high-availability storage by using resource rings. The method forms multiple different resource rings among multiple nodes, and realizes the automatic switching of these resources on the resource rings through corresponding heartbeat technology to realize Storage high availability, including the following steps: 1) start the instance, each instance obtains the configuration file and reads it; 2) each instance obtains the network lock object, and sends an attempt to obtain the lock through the obtained lock object; 3) each instance judges whether to obtain Lock, if yes, then execute step 4), if not, then execute step 5); 4) The master instance continues to send heartbeat information with the set heartbeat interval, and starts and executes the configured resource services one by one; 5) Starts from the instance Timer, to determine whether to receive the heartbeat information sent by the master instance of the resource ring where it is located within the timeout period. Compared with the prior art, the invention has the advantages of saving investment, simple configuration and the like.

The invention discloses a flight time optimization method and system, relating to the field of aviation. The method includes: when a delay occurs at the first flight time, obtaining the set of public resources not released due to the delay at the first flight time; The intersection of the public resource set and the travel necessary resource set at the second flight time is obtained to obtain the target missing resource set at the second flight time; find all necessary resource sets at the subsequent flight time at the second flight time Replacement resources for the missing resources of the target, so that the second flight time can be executed normally. It solves the problem of continuous delay of follow-up flights caused by flight resource occupation caused by flight delays, improves the overall punctuality rate of flights and the utilization rate of flight slots, and reduces the operating costs of flights.

The present application provides a microservice processing method and device, which are applied to a server providing microservices. The method includes: the server receives a message for invoking a microservice from a terminal consuming the microservice, wherein the message includes the service identifier of the target microservice and Interface ID; then the server determines the corresponding target thread pool according to the service ID and interface ID of the target microservice, and finally calls the worker thread in the target thread pool to execute the message. This method can limit the scope of the fault to the thread In the pool, avoid spreading to the entire microservice process, this method has low hardware and operation and maintenance costs.

The invention relates to a coordinated plan compiling and executing method. According to the method, a coordinated compiling zone and an executing zone are first established, and then the following steps are conducted: 1) compiling plans in the coordinated compiling zone; 2) submitting the compiled plans for approval by levels by the coordinated compiling zone; 3) sending the approved plans to the executing zone by the coordinated compiling zone; 4) executing the plans by the executing zone; and 5) feeding back executing information to the coordinated compiling zone after the execution of the executing zone. The method is suitable for the whole plan management mode from beginning to end so that the plans are conveniently compiled, and the information is timely fed back. In concentrated stage compiling, the execution of the plans is not influenced during the compiling, the plans are massively sent to the executing zone to be executed after being compiled, the information is fed back to the coordinated compiling zone after the execution of the executing zone, and the coordinated compiling zone continuously compiles the plans of the next stage. When the work loads of both compiling and execution are large, the burden of a system is shared, and the purpose that a large number of plans are compiled and executed without mutual influence becomes possible.