A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon
receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing
system. These changes become visible upon the processor entering a
Commit operating state in response to
receipt of a
commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to
receipt of the
commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.