320results about How to "Data transfer speed is fast" patented technology

The invention discloses an electronic device and a method and device for implementing coordinated transmission between electronic devices. The electronic device comprises a coordination establishment module configured to send a coordination request signal to candidate coordination devices as well as determine coordination devices in accordance with a response of the candidate coordination device and establish coordination connection with the determined coordination device, and a data transmission module configured to transmit target data by a plurality of communication links, the plurality of communication links comprising communication links between the electronic device and the coordination device. The present invention can establish the coordination connection reasonably by initiating the coordination through the request and transmitting the data through the plurality of communication links by the coordination device, thereby effectively improving the data transmission speed through the plurality of the communication links.

Disclosed is a method for transmitting a signal in a mobile communications system using a plurality of transmit/receive antennas. A method for transmitting a signal in accordance with an embodiment of the present invention comprises the steps of: a receiving end's calculating a signal to interference noise ratio (SINR) with respect to every antenna pairs configuring STTD pairs to be transmittable from a transmitting end; feedbacking information indicating an antenna pair having the greatest SINR to the transmitting end; and the transmitting end's performing a D-STTD transmission through the antenna pair determined by the feedbacked information. A method for transmitting a signal in accordance with another embodiment of the present invention comprises the steps of: a receiving end's feedbacking information of an antenna pair and/or an eigenvector (weight vector) of a channel matrix with respect to transmit antennas included in the space-time multiplexing (STTD) pair to a transmitting end; and the transmitting end's forming beam by multiplying a symbol with respect to each STTD pair by the eigenvector, and thereafter transmitting the beam through each transmit antenna (in case of using two antennas) or a transmit antenna pair (in case of using more than four antennas) determined by the information of the antenna pair.

The invention provides a method of point-to-point data transmission for a mobile device and a device. The method comprises the following steps that: a first mobile device and a second mobile device performs NFC pairing within the effective distance of NFC (Near-Field Communication), and the first mobile device sends wireless broadband (Wireless Fidelity(WIFI)) connection parameters and a file finding list to the second mobile device in the process of NFC pairing; and the first mobile device and the second mobile device utilize the WIFI connection parameters to build WIFI connection; and the first mobile device utilizes the WIFI connection to send one or more files in the file finding list to the second mobile device. The point-to-point data transmission for the mobile devices provided by the invention can achieve the objects of simple operation, increased effective distance, improved stability of connection and improved data transmission speed.

The invention discloses a wisdom skynet video behavior analyzing system which comprises a plurality of front end video collecting systems and a central monitoring system. The central monitoring system comprises a plurality of video behavior analyzing servers, a storage server, a monitoring server and a client side, wherein each video behavior analyzing server receives video information of one front end video collecting system respectively, automatically analyzes all kinds of exception behaviors by the adoption of an advanced image analyzing processing technology, a computer vision technology, a computer network technology and an artificial intelligent technology and generates alarming signals, the video behavior analyzing servers are respectively connected with the storage server, the monitoring sever and the client end through an interchanger, and the monitoring server is further connected with a third party alarm linkage server. The wisdom skynet video behavior analyzing system is provided with multiple detection modules, users can selectively install certain modules according to actual needs, installation is convenient, the operation is simple, and video behavior analysis can be carried out automatically. A distribution type structure is adopted by the wisdom skynet video behavior analyzing system, and data transmitting and processing speed can be improved.

The first storage subsystem, when new data is written in a first memory device beyond a certain timing, writes pre-updated data prior to update by said new data into a pre-updated data memory region and, in addition, updates snapshot management information that expresses a snapshot of a data group within the first memory device to information that expresses the snapshot at the certain timing and, at a later timing than the certain timing, judges, on the basis of the snapshot management information, in which of either the pre-updated data memory region or the first memory device the data constituting the data group at a certain timing exists, acquires data from the one in which the data exists and writes it into the second memory device of the second storage subsystem, and generates the certain timing repeatedly.

An apparatus and method implemented in hardware and embedded software that improves performance, scalability, reliability, and affordability of Storage Area Network (SAN) systems or subsystems. The apparatus contains host computers (application servers, file servers, computer cluster systems, or desktop workstations), SAN controllers connected via a bus or network interconnect, disk drive enclosures with controllers connected via network interconnect, and physical drive pool or cluster of other data storage devices that share I/O traffic, providing distributed high performance centrally managed storage solution. This approach eliminates I/O bottlenecks and improves scalability and performance over the existing SAN architectures. Although this architecture is network interconnect (transport) neutral, additional improvements and cost savings could be made by utilizing existing, of the shelf, low latency and high speed hardware such as Advanced Switching (AS) or Myrinet networks as a transport for data, Small Computer System Interface (SCSI) and other commands and messages. Using AS or Myrinet network as a replacement for Fiber Channel (FC) would significantly reduce the cost of such SAN systems and at the same time boost performance (higher data transfer rates and lower latencies). This invention is about defining hardware and software architectural solution that is specifically designed to eliminate I/O traffic bottlenecks, improve scalability, and reduce the overall cost of today's SAN systems or subsystems. This innovative solution, in addition to it's performance superiority compared to the existing solutions, should also provide 100% compatibility with the all existing Operating Systems (OS), File Systems (FS), and existing applications.

An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.

A unique high performance digital video recorder having a number of novel features. The recorder's electronics are all on a unitary printed circuit board. The recorder also requires at least one hard disk drive and audio and video input analog signals (from a source such as video camera or broadcast media) as well as a suitable monitor for receiving output audio and video analog signals. A external time code generator (i.e., VITC digital clock) is also required for synchronization. Also required are various manual control devices (i.e., panel controls) for mode selection. The electronics of the preferred embodiment comprise A-to-D and D-to-A converters, a hard disk interface, a JPEG compression encoder/decoder, a multi-port DRAM and DMA subsystem, a microprocessor with RS-232 and RS-422 access ports, various working memory devices and bus interfaces and a 16-bit stereo digital audio subsystem. Novel features of the preferred embodiment include use of an index table for disk addresses of recorded frames, a multi-port memory controller in the form of a field programmable gate array (FPGA), loop recording using dual channels, and dynamic JPEG compression compensation.

Disclosed are a high speed wide range RFID tag capable of improving a data transmission speed and a recognition distance between an RFID tag and an RFID reader by controlling a reflected power as multi levels through adjustment of a reflection coefficient in the RFID tag, and a method of controlling the same. The RFID tag includes a data converting unit configured to convert stored RFID serial tag data into a number of multi-level parallel data according to a request of an RFID reader, a reflection coefficient adjusting unit configured to generate a plurality of reflection coefficients corresponding to a number of the converted parallel data, and a transmitting unit configured to transmit a number of the multi-level parallel data according to the generated plurality of tag reflection coefficients through an antenna to the RFID reader.

An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

A data transfer method is disclosed in a multi-chip semiconductor device which comprises a plurality of inter-chip wires. First, a test is conducted to determine whether or not each inter-chip wire is capable of normally transferring data, on circuits arranged on chips between which the inter-chip wire is connected. When an inter-chip wire incapable of normally transferring data exists, the data transfer speed of the buffer circuit that is on the chip on the transmission and that is connected to an inter-chip wire capable of normally transferring data is increased. The buffer circuit, whose data transfer speed has been increased, transfers data which would otherwise be transferred through the inter-chip wire incapable of normally transferring data, together with the data which should be transferred thereby, to the chip on the reception side chip through an inter-chip wire connected to the buffer circuit at the data transfer speed.

In a probe memory device, a technique of realizing consistency of high-density recording and high-speed reading/writing is provided. A recording medium is placed to a probe array chip on which a plurality of probes are arranged in such a way as to maintain a constant spacing thereto by adopting a high-stiffness elastic support structure. The recording medium is equipped with a stage scanner that is driven continuously while drawing a constant trajectory on an X-Y plane almost in parallel to a probe array chip plane. The probes are equipped with respective actuators each being driven in a Z direction almost perpendicular to the X-Y plane. Each of the probes is made to write or read by altering a distance between the probe and the recording medium in parallel processing. The X-Y actuator is controlled so that the probe may continue a predetermined cyclic movement. Moreover, a tracking area is provided in a portion of the recording medium, and a trajectory of the probe by actuation is controlled so as to have a fixed geometry.