52results about "Microinstruction function" patented technology

In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor. The logic is adapted to: define a hardware feature policy for one or more hardware components of a system; and enable and/or disable one or more hardware features of one or more of the hardware components based on the hardware feature policy, wherein the hardware feature policy comprises instructions to enable and/or disable access to the one or most hardware features based on one or more criteria selected from a group consisting of: a feature access schedule, a volume feature access group; a job feature access group; and an user feature access group.

A microprocessor with Booth multiplication, in which several acquisition registers are used. In a first word length, a first acquisition register stores an unsigned ending acquisition of a first multiplier number carried in multiplier number supply data, and a third acquisition register stores a starting acquisition of a second multiplier number carried in the multiplier number supply data. In a second word length that is longer than the first word length, a fourth acquisition register stores a middle acquisition of a third multiplier number carried in the multiplier number supply data. A partial product selection circuit is required for selection of a partial product, to get the partial product from Booth multiplication based on the third acquisition register (corresponding to the first word length) or based on the fourth acquisition register (corresponding to the second word length).

An apparatus includes a luminaire; power input for the luminaire; a modulation circuit for modulating the power input so that light output includes an identifier of the luminaire; and a programmable memory for storing at least one of the identifier of the luminaire and a modulation scheme for modulation of the luminaire to place a signal on the light. A method for modulating light includes storing in programmable memory an identifier for the luminaire, the identifier being used to modulate the light, and/or a modulation scheme for modulation of the luminaire; and changing content of programmable memory to change the identifier and/or the modulation scheme. A method of efficiently deploying the luminaires and identifying their locations to a network is disclosed. A method of multi-factor authentication using authentication data transmitted by modulating the light emitted by a luminaire is also disclosed.

A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.

A containerized storage microservice is described. The containerized storage microservice, and its corresponding architecture, provide an environment wherein an application container accesses containerized storage services through a direct connection. This allows the operating system file system to be effectively bypassed in the provision of storage services. In one example, a library provides a basic file system and is arranged underneath the application container. The library essentially intercepts storage requests and emulates a thin file system. Instead of invoking the kernel of the operating system to process each storage request, the library allows the storage request to bypass the kernel and pass the storage request to the storage microservice. The containerized storage microservices are available in different types, and are configured so that they can be stacked to provide customized sets of storage services to different types of application containers.

An apparatus includes a luminaire; power input for the luminaire; a modulation circuit for modulating the power input so that light output includes an identifier of the luminaire; and a programmable memory for storing at least one of the identifier of the luminaire and a modulation scheme for modulation of the luminaire to place a signal on the light. A method for modulating light includes storing in programmable memory an identifier for the luminaire, the identifier being used to modulate the light, and/or a modulation scheme for modulation of the luminaire; and changing content of programmable memory to change the identifier and/or the modulation scheme. A method of efficiently deploying the luminaires and identifying their locations to a network is disclosed. A method of multi-factor authentication using authentication data transmitted by modulating the light emitted by a luminaire is also disclosed.

In one embodiment, a method includes defining a hardware feature policy for one or more hardware components of a system; and enabling and/or disabling one or more hardware features of one or more of the hardware components based on the hardware feature policy, where the hardware feature policy comprises instructions to enable and/or disable access to the one or more hardware features based on one or more criteria selected from the group consisting of: a feature access schedule; a volume feature access group; a job feature access group; and an user feature access group.

An expandable mobile platform is utilized for receiving and executing a plurality of instructions, each instruction has a target position and a target action. The expandable mobile platform includes a mobile platform and an expandable working mechanism. The mobile platform includes a storage module, a positioning module, an instruction ordering module, and a control module. The storage module is utilized for storing a map data and the instructions. The positioning module is utilized for determining a current position of the mobile platform. The instruction ordering module is utilized for analyzing the current position and a plurality of target positions of the instructions, and aligning the target positions as an instruction serial. The control module is utilized for generating moving control signals to control the mobile platform moving to the target positions and action control signals to control the expandable working mechanism executing the target actions according to the instruction serial.

An apparatus includes a first reservation station and a second reservation station. The first reservation station dispatches a first load micro instruction, and detects and indicates on a hold bus if the first load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the first load micro instruction for execution after a first number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the first load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the first load micro instruction has retrieved the operand.

A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.

An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.

Provided is an arithmetic processing to reduce a number of parts as it is not necessary to prepare an operation device for each input processing logic. A plurality of types of input processing logics is stored in the ROM, and CPU selects one of the plurality of types of input processing logics and executes input processing according to the selected input processing logic. As a result, there is no need to prepare the ECU for each input processing logic, reducing the number of parts.