The invention discloses
physical layer architecture for the terahertz
wireless network. The architecture comprises a transmitting end and a receiving end. The transmitting end comprises a scrambler module, a framer module, a
forward error correction (FEC)
encoder module, a
preamble module, a high-speed
transceiver module, an on-off
keying (OOK) modulation module and a terahertz oscillator; and the reception end comprises a reception
processing module corresponding to the transmitting end, as well as a direct
detector, a high-speed
transceiver and CDR module, a frame
synchronizer module, an FEC decoder module, a de-framer module and a descrambler module. The
physical layer architecture can be used to directly process bit data flow, complex
digital signal processing is avoided, the architecture can be applied to single-channel terahertz high-speed
wireless network as high as 100Gbps magnitude, the structure is simpler, convenience is provided for design of special processors, and the
power consumption and size are easy to control; and the
physical layer architecture can be completely parallel in
technical feasibility, can be realized on the basis of a present horizontal FPGA device, and requirement for hardware performance is lower than that of present architecture.