The invention relates to an FPGA-based (
Field Programmable Gate Array-based) IO (Input / Output)
bus device with an automatic recognition function, and belongs to the technical field of buses. The IO
bus device comprises a CPU (
Central Processing Unit), an FPGA, slot position plates, a parallel
bus, a serial bus and a
field bus, wherein the CPU and the FPGA are used for carrying out data interaction through an external bus, and the FPGA and the slot position plates are interacted through the parallel bus or the serial bus; the CPU and the slot position plates are directly interacted through the
field bus; the FPGA is used for providing a plate address for the CPU and helping the CPU to send and receive data, a state
machine is arranged in the FPGA, and the state
machine can be used for selecting plate interfaces in a circulation mode to read plate information and data signals. The FPGA-based IO bus device has a self-recognition plate
information function, so that the reliability of data interaction is enhanced. The communication among plates is more flexible, and upgrading of a device platform is facilitated. The FPGA serves as a bridge of the CPU and
external data, and the interaction of plate data is carried out through the serial bus and the parallel bus.