30results about How to "High impedance state" patented technology

A dual ported (simultaneous read / write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.

Aspects of the present disclosure are directed to an electronic switchbox for automatically switching between receive and transmit functionalities. In one embodiment, an electronic switchbox automatically switches between receiving electrocardiograph signals and transmitting cardioversion impulses.

Provided is a mixed-mode multi-protocol serial interface driver. The driver can work in the current mode or the voltage mode or work in the two modes at the same time. The driver comprises a circuit used for making an output signal conform to one of a series of selectable electrical interface standards including the CCITT / EIA standards V.35, V.11 / RS-422, V.28 / RS-232 and V.10 / RS-423. When the specific standard is selected for an input signal through mode selection, a proper portion in the circuit can start response. Part of the circuit can not be placed in a high-impedance state, and the part of the circuit is prevented from interfering with the portion, starting the response, of the circuit.

A device consists a disordered relaxation insulator or / and a polyamorphous solid between two or more electrodes. Invented devices can perform passive, logic and memory functions in an electronic integrated circuit.

Circuits, methods and systems are provided to reduce skew between a first digital signal that is transmitted by a first driver circuit over a first signal line, and a second digital signal that is transmitted by a second driver circuit over a second signal line. Skew may be reduced by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the second digital signal transitioning to opposite logical values, and otherwise refraining from sourcing or sinking the additional current to or from the first signal line. Skew may also be reduced between the first digital signal that is transmitted by the first driver circuit over the first signal line and a third digital signal that is transmitted by a third driver circuit over a third signal line by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the third digital signal transitioning to opposite logical values, and to otherwise refrain from sourcing or sinking the additional current to or from the first signal line.

A drive method for an electrophoretic display panel having one electrode as a common electrode and another electrode divided into a plurality of segment electrodes, the drive method having steps of: applying pulses that change between two different potential levels to the common electrode; applying pulses at one of the two potential levels to the segment electrode of a segment that changes display state to produce a potential difference to the pulse applied to the common electrode; applying pulses of the same phase and potential as the pulses applied to the common electrode to the segment electrode of a segment that holds the same display state; and inserting a high impedance state to the pulses applied to the common electrode and the pulses applied to the segment electrode of the segment that holds the same display state when the pulse potential changes.

An array of active pixels comprises rows of pixels and row select lines for selecting rows of pixels. Each active pixel comprises a buffer amplifier for buffering an output of a photo-sensitive element. An output of the buffer amplifier can be selectively put into a high impedance state, by control of the input of the buffer amplifier, when there is a defect in the row select line for that pixel. This allows other rows, which are defect-free, to remain operating as normal. A disable line can be provided for a row of pixels and each pixel can have a switch connected to the disable line. Alternatively, a first supply line powers a row of pixels. Each pixel comprises a reset switch connected between a photo-sensitive element and the first supply line for resetting the photo-sensitive element. The array is configured such that, in the event of a defect in a row select line, the first supply line is set to ground, or a low voltage, and the reset switch is turned on to put the buffer amplifier into the high impedance state.

A low voltage differential signaling generating circuit, which comprises a current source a pair of output nodes for providing a differential signal by virtue of a voltage difference therebetween, first and second differential switch circuitries and a bypass circuitry. The first differential switch circuitry selectively connects the current source to the first output node based on a control signal to cause a current flow from the first output node to the second one. The second differential switch circuitry selectively connects the current source to the second output node based on the control signal to cause a current flow from the second output node to the first one. The bypass circuitry is arranged in parallel to the first and second differential switch circuitries and is selectively switched based on an idle mode signal to prevent a current between the output nodes.

The present invention provides a macrocell for a data processing circuit, comprising macrocell logic, and an interface for connecting the macrocell logic to a bus of the data processing circuit. The interface comprises: an input bus connected to an input bus terminal, an output bus connected to an output bus terminal, and a buffering circuit for buffering the output bus from the macrocell logic. Further, the interface has a mode input terminal for receiving a mode value, the mode value being arranged to control the buffering circuit. The buffering circuit is responsive to a first mode value to enter an inactive state when no data is being output from the macrocell, and is responsive to a second mode value to permanently drive the output bus. Hence, to enable the macrocell to be coupled to a unidirectional bus on the data processing circuit, the second mode value is supplied to the mode input terminal, whilst to enable the macrocell to be coupled to a bidirectional bus on the data processing circuit, the input bus terminal and output bus terminal are connected together externally to the macrocell, and the first mode value is supplied to the mode input terminal.

A multiplexer circuit is composed of several basic unit circuits, which are each supplied with a data signal and select signal. Each output terminal of several basic unit circuits is connected to a common line. Each basic unit circuit is composed of an unmatch detection circuit detecting an unmatch state of the common line and the data signal, a control circuit controlling drive timing of the common line when receiving a state transition of the select signal, and a tri-state buffer driving the common line according to a state of the data signal when an output of the unmatch detection circuit and an output of the control circuit are both in an active state while holds high impedance state when the state other than above is given.

Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.

The present invention discloses a system for buffering the outputs of peripheral devices operating in UTOPIA protocol to allow devices on separate circuit boards connected through long buses, such as backplanes, to communicate with the system controller. Address detection logic stores the peripheral device address and compares it to the UTOPIA bus address signal. When the correct address is recognized in a first clock cycle, a flip flop stores the information for the next cycle. A second flip flop stores the state of the read enable signal. An AND gate detects when the correct address was found and the read enable was de-asserted during the first clock cycle and the read enable and read cell available signals are positive during the current clock cycle and provides a high signal to a third flip flop. On a third clock cycle the third flip flop enables the outputs of a data buffer which then drives the peripheral device data signals on to the read data bus. The third flip flop output and the read enable signal are provided to a second AND gate which feeds back to the third flip flop to maintain its state until the read enable signal is de-asserted. The first flip flop is also used to control a buffer for the read cell available signal from the peripheral device. The third flip flop is also used to control a buffer for the read start of cell signal from the peripheral device.

A tri-state buffer made of low voltage complementary metal oxide semiconductor (CMOS) includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

A ferroelectric memory device, in which wordlines and bitlines are hierarchized and influence of disturbance-noise is reduced, includes: first sub-wordline select switches, each of which are disposed between one of the main-wordlines and one end of one of the sub-wordlines provided for the one main-wordline; first sub-bitline select switches, each of which are disposed between one of the main-bitlines and one end of one of the sub-bitlines provided for the one main-bitline; second sub-wordline select switches, each of which are disposed between the other end of one of the sub-wordlines and the unselected wordline potential supply line; and second sub-bitline select switches, each of which are disposed between the other end of one of the sub-bitlines and the unselected bitline potential supply line, each of the first and second sub-wordline select switches and first and second sub-bitline select switches being driven independently at least in one of the sector regions.

A reset circuit comprising: a first depletion mode device having a first terminal coupled to a node at a reset voltage and a second terminal for providing a reset signal to at least one device; and a control circuit arranged to switch the first depletion mode device into a high impedance state after a first predetermined period.