Tri-state buffer prepared from low voltage complementary metal oxide semiconductor

Abstract

A tri-state buffer made of low voltage complementary metal oxide semiconductor (CMOS) includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

Description

technical field [0001] The present invention relates to a buffer (Buffer) made of low-voltage Complementary Metal Oxide Semiconductors (CMOS), and in particular to a Tri-State Buffer made of CMOS. Background technique [0002] Please refer to figure 1 , which represents the circuit diagram of a conventional low-voltage CMOS-fabricated buffer. The buffer 100 includes a biasing device 102 and a switching device 104 . The bias device 102 receives an input signal Vin, and controls the control signals VG5 and VG6 of the transistors T5 and T6 according to the input signal Vin. The bias device 102 biases the control signal VG5 to a specific voltage level through the transistors T1-T4 when the input signal Vin is at a high voltage level, so that the voltage on the gate oxide layer (OxideLayer) of the transistor T5 is less than the low voltage level. Voltage Complementary Metal-Oxide Semiconductor Fabricates the voltage across the gate oxide of transistors. The transistors T5 and...

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Problems solved by technology

In this way, the buffer 100 consumes more power due to continuous current generation

In addition, when the control signal VG5 is to be discharged from the highest voltage level to a low voltage level, the transistors T3 and T4 on the discharge path must bias the control signal VG5 with the transistor T1, so that the size of the transistors T3 and T4 is limited. , so that the discharge current for discharging the control signal VG5 is limited

In this way, the falling time (Falling Time) of the voltage level of the control signal VG5 will be longer, so that the switching device 104 is prone to malfunction

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