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53results about How to "Depth is minimized" patented technology

Fiber optic receptacle and plug assemblies with alignment and keying features

A fiber optic receptacle and plug assembly comprising a fiber optic receptacle adapted to be mounted within a connector port of a network connection terminal and a fiber optic plug mounted upon an end of a fiber optic cable, wherein the fiber optic receptacle and the fiber optic plug comprise complimentary alignment and keying features that allow the fiber optic receptacle to receive only a fiber optic plug of like ferrule configuration. The fiber optic plug comprises an alignment sleeve operable for receiving and optically connecting at least one plug ferrule and at least one receptacle ferrule. The receptacle is suitable for use in enclosures requiring a minimal receptacle penetration depth, wherein the fiber optic receptacle comprises a shoulder that is secured against an inner wall of the enclosure to provide strain relief against cable pulling forces of up to about 600 lbs.
Owner:CORNING OPTICAL COMM LLC

Passive dual-phase cooling for fuel cell assemblies

InactiveUS20060088746A1Improved temperature uniformityReduce cool plate thicknessMaterial nanotechnologyFuel cells groupingChannel widthHeat transfer fluid
A cooling apparatus for a fuel cell assembly includes a heat transfer fluid and at least one fluid flow field plate configured to facilitate essentially passive, two-phase cooling for an membrane electrode assembly (MEA) as the MEA is subject to changes in heat flux to the heat transfer fluid from about 0 W / cm2 to about 1.5 W / cm2. The flow field plate includes fluid flow channels that have a channel depth, a channel spacing, a channel length, and a channel width, which are dimensioned to promote nucleated boiling of the heat transfer fluid below a critical heat flux and to prevent dryout as the heat transfer fluid passes along the length of the channels. The channels may include coatings and / or features, such as microporous or nanostructured coatings, that extend the critical heat flux and preclude dryout at the distal sections of the fluid flow channels.
Owner:3M INNOVATIVE PROPERTIES CO

Method for forming a filled trench in a semiconductor layer of a semiconductor substrate, and a semiconductor substrate with a semiconductor layer having a filled trench therein

A method for forming an isolation filled trench (25) in a silicon layer (21) of an SOI structure (20). The trench (25) is relieved adjacent its open mouth (30) in order to displace the commencement of bridging of the trench (25) with the filling material, to a level (36) well below a first surface (27) of the silicon layer (21) for in turn displacing voids (35) from the open mouth (30) into the trench (25) below the level (36). The trench may be relieved by forming tapered portions (40) in the side wells (29) adjacent the open mouth (30), and / or by relieving one or more lining layers (32) in the trench (25) adjacent the open mouth (30) to form tapered portion (52) and (53). Instead of relieving the trench (25) by tapering the side walls (29) relieving recesses may be formed into the first surface (27) of the silicon layer (21) adjacent the open mouth (30). By relieving the trench (25) or one or more of the lining layers (32) adjacent the open mouth (30) the commencement of bridging of the trench with the filling material is displaced downwardly to a level (36), which displaces voids formed in the trench below the level (36). By sufficiently relieving the trench (25) and / or lining layers (32) adjacent the open mouth to a sufficient depth the formation of voids in the trench may be completely avoided.
Owner:ANALOG DEVICES INC

Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby

Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.
Owner:SAMSUNG ELECTRONICS CO LTD

Method for fabricating semiconductor device with recessed channel region

Disclosed is a method for fabricating a semiconductor device with a plurality of recessed channel regions. This method includes the steps of: forming a plurality of device isolation layers in a substrate; forming a hard mask nitride layer, a hard mask oxide layer and a hard mask polysilicon layer on the device isolation and the substrate, thereby obtaining a hard mask pattern; forming a plurality of trenches in the predetermined regions of the substrate with use of the hard mask pattern to expose a plurality of recessed channel regions; selectively removing the hard mask pattern; and forming a plurality of gate structures in the plurality of trenches.
Owner:SK HYNIX INC
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