An apparatus including a JTAG interface, synchronous
bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to
delay a data bit
signal associated with a second data group. The synchronous
bus optimizer receives the control information, and develops a first value on a first ratio
bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe
clock by the first amount. The synchronous strobe driver employs the data strobe
clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit
signal, delayed by the second amount.