38 results about "Re-order buffer" patented technology

Disclosed are an execution method of a Packet Data Convergence Protocol (PDCP) entity and a corresponding entity apparatus. The method includes: mapping a PDCP Protocol Data Unit (PDCP PDU) which is received from a lower entity of a PCDP entity and arrives in disorder onto a PDCP Service Data Unit (PDCP SDU) and storing PDCP SDU in a reorder buffer; judging whether the serial number of a missing PDCP SDU is smaller than the smaller one of the biggest serial number of the PDCP SDUs respectively received from two lower entities by the PDCP entity; and if the serial number of the missing PDCP SDU is smaller than the smaller one, delivering to a higher layer entity of the PDCP entity the PDCP SDU stored in the reorder buffer with the serial number smaller than the serial number of the missing PDCP SDU, and the PDCP SDU with the serial number bigger than the serial number of the missing PDCP SDU and continuous with the missing PDCP SDU.

In the data transmission method of an HSDPA system according to the present invention, a transmitter transmits Data Blocks each composed of one or more data units originated from a same logical channel, and a receiver receives the Data Block through a HS-DSCH and distributes the Data Block to a predetermined reordering buffer. Since each Data Block is composed of the MAC-d PDUs originated from the same logical channel, it is possible to monitor the in-sequence delivery of the data units, resulting in reduction of undesirable queuing delay caused by logical channel multiplexing.

These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.

A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after out-of-order execution when at least one of the plurality of processors is in an Instruction Level Parallelism (ILP) mode and at least one of the plurality of processors has a Thread Level Parallelism (TLP) core; detecting an imbalance in a dispatch of instructions of a first dependence chain compared to a dispatch of instructions of a second dependence chain with respect to dependence chain priority; determining a source of the imbalance; and activating the ILP mode when the source of the imbalance has been determined.

A method for HARQ reordering in Enhanced Uplink Dedicated Channel of WCDMA system includes following steps: locating the soft combination buffer in the Node B and the reordering buffer in the SRNC; locating the HARQ entity in the Node B; locating the reordering queue distribution entity, the reordering entity and the disassembly entity in the SRNC. This invention adopts the separation technology of the soft combination buffer and the reordering buffer, the separation model can not only ensure the diversity gain, but also reduce the receiving delay and save the buffer space. Three mechanisms (timer mechanism, window mechanism and SBI mechanism) are proposed to prevent the blocking of the reordering buffer, which degrades the blocking to the least level, improves the receiving efficiency and the system performance. Aiming at the SBI mechanism, the invention proposes the new DCH data frame structure on the Iub interface and the Iur interface.

Bounding cell reorder depth is disclosed. It is determined whether a reorder buffer that is associated with a switch fabric exceeds a depth limit. In the event that the reorder buffer exceeds the depth limit, backpressure with respect to a source associated with the reorder buffer is sent. In such cases source based back pressure information is included in a reserved field in a cell that is being sent into the switch fabric. In the event that the reorder buffer does not exceed the depth limit, the cell is sent to the switch fabric. In such cases the reserved field is present in the cell but is unused.

Embodiments of an apparatus, method, and system provide for no-operation instruction (“NOP”) folding such that information regarding the presence of a NOP instruction in the instruction stream is folded into a buffer entry for another instruction. Information regarding a target NOP instruction is thus maintained in a buffer entry associated with an instruction other than the target NOP instruction. For at least one embodiment, NOP information is folded into entries of a re-order buffer.

Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

By using an entry number (WRB number) of a re-order buffer 6, each of function units such as an operation unit 3, a store unit 4, a load unit 5, etc. notifies to the re-order buffer 6 the processing end for a instruction stored in the entry concerned in the unit thereof. The load unit 5 manages the latest speculation state of a load instruction issued on the basis of a branch prediction success / failure signal output from the branch unit 2, and makes no notification to the re-order buffer 6 on the basis of WRB number for subsequent load instructions of a branch-prediction failed branch instruction even when the processing of the instruction is finished. Accordingly, the re-order buffer 6 can re-use entries in which the subsequent instructions of the branch prediction failed branch instruction are stored.

A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.

A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the L2 cache may be returned out of order, the L1 cache uses it's cache memory to buffer the out of order data and provides the data to the requesting processor in the correct order from the buffer.

Aspects relate to arbitrating access to an interconnect among multiple ports. For example, input ports receive requests for access to identified destination ports and buffer these in one or more FIFOs. A picker associated with respective FIFO(s) begins an empty arbitration packet that includes a location for each output port and fills one or more locations in the packet, such as based on a prioritization scheme. Each packet is passed in a ring to another picker, which performs a fill that does not conflict with previously filled locations in that packet. Each picker has an opportunity to place requests in each of the packets. Results of the arbitration are dispatched to reorder buffers associated with respective output ports and used to schedule the interconnect. Each arbitration cycle thus produces a set of control information for an interconnect to be used in subsequent data transfer steps.

A re-order buffer memory in a real-time application such as e.g., an imager. Initially, input data is written into the re-order buffer using a first addressing mode, which causes the data to be stored in a line-by-line manner. Prior to receiving the last line of input data, the stored data is read-out in blocks of data that spans multiples lines in the buffer. This frees up space in the re-order buffer. Subsequently received input data is written into the re-order buffer using a second addressing mode, which stores the newly received data in vertical segments of the re-order buffer whose stored data has already been read-out. Writing / reading of the re-order buffer alternates between the first and second addressing modes. Using this technique, a single buffer may be used to input new data while existing data is being read-out.

A processor may include a reorder buffer, reservation stations, and execution units. The reorder buffer may be a circular buffer with a head pointer and a tail pointer, configured to assign indexes to instructions. Reservation stations may be configured to host instructions with the assigned indexes, while waiting to be issued to the execution units. Responsive to exception event, reservation stations may be configured to flush instructions that are younger, in program order, than the instruction executed with exception. Execution units may provide the reorder buffer index EX of the instruction executed with exception. The reorder buffer may provide the reorder buffer index TP stored in the tail pointer. Reservation stations may be configured to flush instructions with assigned indexes in the wrapped-around increasing interval from the index EX to the index TP.

Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

A technique for restoring a register renaming map is described. In one example, a restore table with multiple storage locations holds a copy of the register renaming map whenever a flow risk instruction is passed to the reorder buffer. When all storage locations are full, further instructions are still passed to the reorder buffer, but no copy of the mapping is kept. A storage location then becomes available when the process risk instruction associated with that storage location is executed. A state of a register rename map for unrecorded flow-risk instructions passed to the reorder buffer when the plurality of memory locations are full is generated and stored in the available locations. The state of the register renaming map is generated using a restore table entry for a previous flow-risk instruction and a reorder buffer value for an intermediate instruction between the previous flow-risk instruction and the Between the above undocumented process risk instructions. The restore table can be used to restore the mapping if an unexpected change occurs in the instruction flow.

The invention provides an instruction classified multi-emitting method based on an SPRAC V8 (Scalable Processor Architecture V8) instruction set. According to the method, SPARC V8 instructions are divided into four classes; an SPRAC V8 processor is divided into five flow stages including an instruction fetching stage, a decoding stage, an execution stage, a memory accessing stage and a writing-back stage; the five flow stages are connected through a common data bus; (n-1) instruction fetching paths are added at the instruction fetching stage; (n-1) decoding units are added at the decoding stage; n groups of reservation stations are added between the decoding stage and the execution stage; reordering buffer regions are added between the execution stage and the memory accessing stage; corresponding execution units are added in the execution stage; a multi-emitting five-stage flow line structure is built for the SPRAC V8 processor; the conflict among parallel instructions is detected through the reservation stations; different instructions are processed through different execution units; finally, the instruction execution results are sequentially submitted by the reordering buffer regions; the parallel execution of the instructions is realized; and the processing performance of the SPRAC V8 processor is improved.