50 results about "Matrix entry" patented technology

A system and a method are disclosed for synchronizing folders between one or more layers of folders. It includes selecting layers to link together, comparing folders in the selected layers using an immutable identifier, parsing the folders of each of the selected layers into fields, comparing the fields of parsed folders of the selected layers, and determining whether to synchronize the folders of the selected layers based on conflict rules triggered in response to the comparison of the fields of the parsed folders. Also disclosed is a system and method of merging two or more folders in a network into a single folder. It includes comparing entries between folders to identify duplicate entries, grouping the identified duplicate entries in each folder, generating a matrix from the duplicates grouping and assigning each matrix entry a value, and matching the matrix entries based on the assigned values to determine an extent to merge an identified duplicate entry.

A system and a method are disclosed for synchronizing folders between one or more layers of folders. It includes selecting layers to link together, comparing folders in the selected layers using an immutable identifier, parsing the folders of each of the selected layers into fields, comparing the fields of parsed folders of the selected layers, and determining whether to synchronize the folders of the selected layers based on conflict rules triggered in response to the comparison of the fields of the parsed folders. Also disclosed is a system and method of merging two or more folders in a network into a single folder. It includes comparing entries between folders to identify duplicate entries, grouping the identified duplicate entries in each folder, generating a matrix from the duplicates grouping and assigning each matrix entry a value, and matching the matrix entries based on the assigned values to determine an extent to merge an identified duplicate entry.

Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which a left-hand portion of the parity check matrix is arranged as an identity macro matrix, each entry of the macro matrix corresponding to a permutation matrix having zero or more circularly shifted diagonals. The encoder circuitry includes a cyclic multiply unit, which includes a circular shift unit for shifting a portion of the information word according to shift values stored in a shift value memory for the matrix entry, and a bitwise exclusive-OR function for combining the shifted entry with accumulated previous values for that matrix entry. Circuitry for solving parity bits for row rank deficient portions of the parity check matrix is also included in the encoder circuitry.

An apparatus and method causes a response action in an electrical power distribution system having, inter alia, a plurality of intelligent electronic devices (IEDs) configured to provide protective monitoring and control of the electrical power system. The method includes detecting receipt of one of a number of matrix input signals that can be received from the plurality of IEDs, and comparing the matrix input signal to a configuration of a m×n cross-point switch matrix having a corresponding number of A[m,n] entries. Each of the n rows is associated with a matrix input signal and each of the m columns is associated with one of a number of matrix output signals that can be transmitted to the plurality of IEDs. The method also includes asserting a matrix output signal based on the comparison to cause the response action.

A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator "s". The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.

An apparatus and method causes a response action in an electrical power distribution system having, inter alia, a plurality of intelligent electronic devices (IEDs) configured to provide protective monitoring and control of the electrical power system. The method includes detecting receipt of one of a number of matrix input signals that can be received from the plurality of IEDs, and comparing the matrix input signal to a configuration of a m×n cross-point switch matrix having a corresponding number of A[m,n] entries. Each of the n rows is associated with a matrix input signal and each of the m columns is associated with one of a number of matrix output signals that can be transmitted to the plurality of IEDs. The method also includes asserting a matrix output signal based on the comparison to cause the response action.

The invention discloses a video advertisement detecting method based on an explicit type sharing subspace, belonging to the technical field of multimedia index. The method comprises the steps of: firstly, cutting the lens to a semantic lens sequence; extracting a key frame therein and obtaining the visual feature and an audio feature, further obtaining the explicit type sharing subspace and the feature value of a mapping matrix formed by both; then obtaining the visual feature mapping matrix and the audio feature mapping matrix via selecting the corresponding vector of the feature value of the pointed mapping matrix in the explicit type sharing subspace; realizing the operation of reducing dimensions and fusing features; inputting the matrix obtained by fusing features to a support vector machine to train; after obtaining the optimal classification model, performing the primary judgment on the lens to be detected by using it; and then confirming whether the lens to be detected is the advertisement lens finally via the step of the post treatment. The invention is not required to build the advertisement database; the vector playing the main role is used for detecting the lens; at last, the lens is judged via the step of post treatment, and therefore improving the effectiveness and the accuracy of detecting.

Light distortion due to light noise or light scattering object in the path of a light beam from a projector to a camera's image sensor in projector-camera systems are mitigated, or eliminated, by a simple modification to a light transport matrix T. For each row in light transport matrix T, matrix entries along a common row are compared, and all but the highest valued entry in the row are zeroed out, i.e. nullified. It is preferred that an array and record notation be used in order to reduce the size of the light transport matrix T, and its modified version to two arrays.

It is disclosed a switch for telecommunication networks. It comprises: a time division multiplexing matrix provided with a number of matrix inputs and a number of matrix outputs; source address generators, connected to matrix outputs of the time division multiplexing matrix. It further comprises: input modules, each of said input modules being adapted to generate a fixed size block, said block comprising a number of packets, arranged according to a predefined order; matrix input processing modules, each of said matrix input processing modules being connected to an input module to receive therefrom said fixed size block, and each of said matrix input processing modules being further connected to a matrix input; and a dynamic provisioning module, which is adapted to receive from said matrix input processing modules routing information comprised in said packets, generate, according to said routing information, a dynamic routing table, and supply said dynamic routing table to the source address generators.

A method of managing large scale biometric data identity matching includes identifying a plurality of biometric modalities to be used in conducting identity matches, determining one of the biometric modalities to be a primary biometric modality and determining whether at least one matching algorithm is compatible with matrix entries. When the at least one matching algorithm is compatible with a matrix entry the method includes assigning a plurality of matching systems to the matrix entry. The matching systems are configured to conduct 1:1 or 1:few matching after conducting a 1:N identity matching. Furthermore, the method includes comparing a probe against enrollment data records stored in a corresponding matching system, and storing information regarding a matching enrollment data record in a queue when the probe matches an enrollment data record.

The invention discloses a method for predicting the power quality of a power distribution network including distributed generation based on a support vector machine. The method comprises the steps ofinputting a PQ data matrix, and dividing the data matrix into a test set matrix and a verification training set; further dividing the verification training set into a training set and a verification set; performing data normalization processing; obtaining optimal c and g parameters in each set division mode based on a grid searching method, obtaining an optimal set division mode based on a K-foldcross verification method, and finishing parameter optimization of a support vector machine model; carrying out power quality prediction on the basis of a built optimal PQ prediction model; and calculating a relative error value of a prediction result.

A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator “s”. The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.

One embodiment of the invention provides a text keyword generating method and device and an electronic device and a readable storage medium, which can be applied in the technical field of multimedia. The method comprises following steps: obtaining a text to be detected, performing vector representation on each character in the text to be detected to obtain a character matrix of the text to be detected; inputting the character matrix of the text to be detected into a pre-established keyword model to obtain a keyword matrix corresponding to the character matrix of the text to be detected; calculating the similarity between each vector in the keyword matrix and a character vector in the vector model, and obtaining a keyword of the text to be detected according to the similarity. The keyword model is obtained by training the training data through long and short term memory LSTM neural network. The training data comprises: a character matrix for a sample text and a keyword matrix of keywords in the sample text corresponding to the character matrix. The embodiment of the present invention improves the accuracy of text keyword generation.

The present invention provides a method and apparatus for implementing a matrix algorithm for scheduling instructions. One embodiment of the method includes selecting a first subset of instructions so that each instruction in the first subset is the earliest in program order of instructions associated with a corresponding one of a plurality of sub-matrices of a matrix that has a plurality of matrix entries. Each matrix entry indicates the program order of one pair of instructions that are eligible for execution. This embodiment also includes selecting, from the first subset of instructions, the instruction that is earliest in program order based on matrix entries associated with the first subset of instructions.

The present invention provides a method and apparatus for implementing a matrix algorithm for scheduling instructions. One embodiment of the method includes selecting a first subset of instructions so that each instruction in the first subset is the earliest in program order of instructions associated with a corresponding one of a plurality of sub-matrices of a matrix that has a plurality of matrix entries. Each matrix entry indicates the program order of one pair of instructions that are eligible for execution. This embodiment also includes selecting, from the first subset of instructions, the instruction that is earliest in program order based on matrix entries associated with the first subset of instructions.

The invention relates to a FPGA (Field Programmable Gate Array) implementation device for solving least square problem based on Cholesky decomposition, which is suitable for solving the least square problem and settles the problem that computation efficiency of PC (Personal Computer) cannot satisfy real-time and embedded applications; the device comprises a to-be-solved matrix input interface module, a decomposing module and a solving module, wherein an output end of the to-be-solved matrix input interface module is connected to an input end of the decomposing module, and the output end of the decomposing module is connected to the input end of the solving module in order to satisfy real-time, low-consumption and embedded applications.

The invention provides a bug report-oriented fine-grained defect positioning method in the field of software maintenance. The method comprises the following steps: firstly, obtaining a defect description feature vector based on a historical bug report, and constructing a high-frequency word corpus; extracting code blocks where defects are located, and constructing a code semantic matrix; inputtingthe feature vector and the code semantic matrix into a neural network to obtain a prediction model; training according to programs with similar functions to obtain a neural network model; replacing semantically similar words of the new bug report once, inputting the replaced feature vector into a prediction code construction model, and outputting a code semantic matrix; dividing a source code corresponding to the new bug report into code basic blocks, and respectively encoding the code basic blocks into code semantic matrixes to form a code semantic matrix list. According to the software defect repairing method, the defect positioning range is accurate to the basic code block level, and software defect repairing work can be more efficient.

The invention discloses a large-scale MIMO linear detection hardware framework under a non-ideal communication channel. A channel response matrix is enabled to sequentially pass through a triangular pulsation multiplication module and a noise addition module, and enters into a three-diagonal inversion module and a three-diagonal multiplication module. The three-diagonal inversion module selects three-diagonal elements in a matrix outputted by the noise addition module to form a three-diagonal matrix, and carries out the inversion calculation of the three-diagonal matrix. The triangular pulsation multiplication module enables the matrix, which is outputted by the noise addition module, after three diagonals are removed to multiply with a three-diagonal inversion matrix obtained from the three-diagonal inversion module. The results of the three-diagonal inversion module are inputted to a three-diagonal addition module, and the results of the three-diagonal multiplication module are inputted to a lower triangular pulsation multiplication module. The three-diagonal addition module and the lower triangular pulsation multiplication module enable a generated matrix to be inputted to a detection module after loop iteration. The framework reduces the hardware complexity, greatly reduces the calculation complexity, and greatly reduces the throughput rate.

The invention discloses a signature authenticity identification system for a signature pen. The system comprises an information entry module, a sample database module, a feature model building module,a feature extraction module, a similarity measurement module and an identification and output module. The identification process is that the feature model building module carries out spatial modelingon feature information collected by the information entry module, the feature parameters of relationship of two types of features including writing horizontal pressure and a holding pen posture withtime and handwriting length are extracted from a spatial geometric model, and a matrix input system is constructed. The average information entropy of each type of features is used to calculate a weight coefficient, and a comprehensive feature similarity of information to be measured and sample information are calculated with the combination with a method of matrix similarity measurement. In the identification and output module, the comprehensive similarity and similarity thresholds corresponding to different signers are compared, and the authenticity of a signature is identified and a final authentication result is outputted. The invention provides signature authentication and identity authentication methods, and the result is objective and stable.

A processor may create a preference vector by generating preference vector entries in fields that correspond to content attributes associated with at least one media program presented via a media device, each entry including a playback duration and a year. The processor may create a media entity matrix of entity vectors for entities associated with production of media programs. For each entity vector, the processor may generate matrix entries in fields that correspond to content attributes associated with at least one media program associated with the entity, each matrix entry including a year and a score, the score weighted by an epoch factor based upon a time span associated with the at least one media program presented via the media device. The processor may determine entity rankings based upon dot products between the preference vector and the entity vectors and provide a recommendation based upon the rankings.

The invention discloses a two-dimensional contour layout and sequencing method based on deep learning, which comprises: acquiring the layout history big data and pre-processing, and calibrating all the arranged parts in the historical data to obtain a layout order matrix Y. Extract the geometric features of each sampled part to obtain the geometric feature matrix X; sorting out the sampled sequence data set PRD-T; building the deep learning model Packing-Sort-Model; inputting the PRD-T data set, and traiiung to obtain, wherein The model Packing-Sort-Model that outputs the order of the parts tobe sampled; extracting the geometric features of the parts to be sampled, obtaining the geometric feature matrix A of the parts to be sampled; inputting the geometric feature matrix of the parts to be placed into the trained In the deep learning model; calculate the layout order matrix B of the parts to be placed; perform the nesting one by one according to the layout order, and complete the layout. The invention can realize the ordering of the parts to be discharged during the layout process, and has good layout effect and high efficiency.

Minimizing memory access by converting a given matrix computation into a set of low-order polynomials. The low-order polynomials can be used by dividing the domain of the polynomials into smaller subregions. If the domain is divided into equal intervals, the low-order polynomial can be used to approximate results from the matrix computation. The set of polynomials is processed using parallel computational hardware such as graphical processing units.

The invention discloses a method and a device for forecasting the heat load of a power system. The method comprises the following steps: S1, preprocessing the historical data of the heat load of the power system; S2, obtaining a data day reference line according to the historical daily data after the preprocessing; S3, dividing the obtained data daily reference line into a plurality of time periods; S4: screening the historical day data, and calculating the trend similarity value of the selected historical day data and the data day datum line in each divided time period; 5, selecting the historical day data corresponding to the trend similarity value great than the preset reference value to form a similarity sequence matrix; S6: the similarity sequence matrix is inputted into the constructed limit learning machine ELM for training, and the prediction model is obtained, and the power system heat load prediction is carried out. The invention adopts the time sequence representation methodbased on trend segmentation, effectively retains the important change trend information in the time series of the heat load, and can more accurately predict the change trend of the heat load.

Light distortion due to light noise or light scattering object in the path of a light beam from a projector to a camera's image sensor in projector-camera systems are mitigated, or eliminated, by a simple modification to a light transport matrix T. For each row in light transport matrix T, matrix entries along a common row are compared, and all but the highest valued entry in the row are zeroed out, i.e. nullified. It is preferred that an array and record notation be used in order to reduce the size of the light transport matrix T, and its modified version to two arrays.

Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.

The invention discloses a fingerprint epipole accurate positioning method based on an image spatial domain characteristic. The method comprises the following concrete steps: solving a pixel-grade direction field O of a fingerprint image by use of a gradient method; extracting each coarse epipole position in the direction field O by use of a Poincare index method; calculating a binary image I of the fingerprint image by use of a short time Fourier transform method; inputting the direction field O, the coarse epipole positions and the binary image I into a bifurcation aggregation extraction module, and extracting all bifurcation points fc and aggregation points gh within an a*b rectangular scope nearby the coarse epipole positions for storing in a matrix FJi; inputting the matrix FJi into a denoising module to remove all pseudo bifurcation points and pseudo aggregation points of the matrix FJi so as to obtain a matrix FJi<->; inputting the matrix FJi<-> obtained after denoising into an arc extraction module to obtain all arcs, and storing the obtained arcs in a matrix Hu; and inputting the matrix Hu into a precision positioning module to obtain a final result of epipole positioning. According to the invention, spatial domain information of the fingerprint image is utilized, and the detection precision is improved while the epipole detection consistency is maintained.

A method and system for entering Chinese characters into a computer by entering the size and shape of their strokes via a matrix, such as the 3×3 arrangement of the numbers one through nine found on a cell phone.

The invention discloses an Android malicious software efficient detection method and a system based on runtime data analysis, and a medium. After an APP is run, behavior operation of a person on the APP is simulated, tracked and recorded, and running data of the APP is generated; extracting the operation data of the APP through a heterogeneous information network HIN to obtain structured data of the operation data of the APP, and forming a kernel matrix in a meta-path mode; and inputting the kernel matrix into a pre-trained machine learning classifier to obtain a detection result. According tothe invention, the behavior data of the APP is extracted by using a dynamic feature extraction technology; according to the method, the extracted APP behavior data is subjected to structured processing through the heterogeneous information network (HIN), the structured data forms a kernel matrix in a meta-path mode, and training is performed by using a support vector machine (SVM) classifier, sothat very short training time and relatively high accuracy can be realized.

The invention discloses a face recognition method based on dictionary learning models. The method comprises the following steps of: mapping trained and tested face images to a low-dimension space to acquire a training signal set matrix; establishing the dictionary learning models which comprise an irrelevant dictionary learning (IDL) model and an unconstrained irrelevant dictionary learning (U-IDL) model; inputting the training signal set matrix into the IDL and U-IDL models, and solving the models to acquire an irrelevant dictionary and a linear classifier; acquiring a corresponding sparse vector of each picture belonging to a test sample based on the dictionary acquired in the last step by using a sparse expression algorithm; and inputting the sparse vectors into the linear classifier to acquire category labels of test sample pictures, wherein the result expressed by the category labels is used as the face recognition result. The invention provides the new models and the new method for dictionary learning problems in sparse expression, and the models and the method can be applied to mode identification and image classification problem under common conditions; and particularly, aiming at face recognition application, the dictionary learning method can achieve relatively high face recognition accuracy.