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339 results about "Logical Function" patented technology

The OR function is a basic logical function that is used to compare any two statements or values. If you’re familiar with any kind of programming language, you have most probably used it before.

In service programmable logic arrays with low tunnel barrier interpoly insulators

Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source / drain region and a second source / drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and / or a Perovskite oxide tunnel barrier.
Owner:MICRON TECH INC

Inter-chip and intra-chip wireless communications systems

A method and implementation for communicating between logic functions using non-metallic coupling between logic functions on a same chip or separate chip is shown. For communication on the same chip, radiated energy from an antenna coupled to a transmitting logic function is coupled to a receiving antenna and then coupled by an electrical connection to a receiving logic function. Communication between USLI chips mounted on a module is performed by coupling an RF signal from a first chip to a μ-satellite mounted within the module and then coupling the RF signal from the satellite to a second chip. Communication can also be formed between the satellite and different logical functions on the same USLI chip.
Owner:NANYANG TECH UNIV

Query Execution and Optimization Utilizing a Combining Network in a Parallel Computer System

An apparatus and method for a database query optimizer utilizes a combining network to optimize a portion of a query in a parallel computer system with multiple nodes. The efficiency of the parallel computer system is increased by offloading collective operations on node data to the global combining network. The global combining network performs collective operations such as minimum, maximum, sum, and logical functions such as OR and XOR.
Owner:IBM CORP

Service programmable logic arrays with low tunnel barrier interpoly insulators

Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source / drain region and a second source / drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and / or a Perovskite oxide tunnel barrier.
Owner:MICRON TECH INC

Digital integrated circuit chip testing system

The invention provides a test pattern-based testing system for realizing a functional test on a digital integrated circuit. The functional test is mainly used for testing logical functions of a chip under a certain timing sequence, and a basic principle is that the chip is excited by means of test patterns and whether the response of the chip is consistent with expected response is observed. The functional test can cover failure models of extremely high proportion logic circuits. A debugging technology supported one-step testing system comprises two parts, namely test pattern file conversion software applied to a personal computer (PC) and a digital integrated circuit chip testing machine, wherein the digital integrated circuit chip testing machine consists of architectures of a central processing unit (CPU) and a field programmable gate array (FPGA); the CPU is used for storing and converting pattern files, controlling the testing process, communicating with a host, and the like. A pattern controlling logic circuit is realized by an FPGA, the waveform generation, the control of Pattern random access memory (RAM) and sampling control are finished through the FPGA, and a drive and a comparator are controlled so as to test and control a tested object.
Owner:BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD

Variable threshold transistor for the Schottky FPGA and multilevel storage cell flash arrays

An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions. It acts as an analog device to store directly nonvolatile information in SCL gates. It couples the diode tree logic functions. Finally, it stores and operates large amount of information efficiently. The mixed SCL type FPGA and MLC storages shall emerge as the most compact logic and memory arrays in Si technology. Low power, high performance, and high capacity ICs are designed to mix and replace conventional CMOS-TTL circuits. The idea of multi-value logic composed of binary, ternary, and quaternary hardware and firmware is also introduced.
Owner:SUPER TALENT ELECTRONICS

Programmable logic arrays with ultra thin body transistors

Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. Each logic cell further includes at least one single crystalline ultra thin vertical transistor that is selectively disposed adjacent the vertical pillar. The single crystalline vertical transistors have an ultra thin single crystalline vertical first source / drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source / drain region coupled to the second contact layer; and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source / drain regions.
Owner:MICRON TECH INC

Multifunctional integrated configuration platform system of secondary equipment of intelligent substation

The invention discloses a multifunctional integrated configuration platform system of secondary equipment of an intelligent substation. The multifunctional integrated configuration platform system of the secondary equipment of the intelligent substation comprises a sampling interface independent configuration module, a substation logical configuration module, an IEC 61850 project configuration module, an SV sampling value sending configuration module and a digital relay protection equipment platform, wherein the digital relay protection equipment platform comprises an analog quantity and fiber interface module, a common IO and operation box interface module, a protection measurement and control logical function module, a station control layer MMS service module, a GOOSE communication service module and an SV sampling value sending service module. The multifunctional integrated configuration platform system can be used in the intelligent substation, realizes the functions of an independent protection, measurement and control device, a merging unit device, an intelligent unit device and a two-to-one or multi-to-one functional device, realizes the integration of the functions of the secondary equipment of the intelligent substation and project configuration, simplifies equipment configuration inside the substation, optimizes a network structure of the intelligent substation, effectively improves the operation reliability and project designing and debugging efficiency of the whole system.
Owner:STATE GRID CORP OF CHINA +3

Flexible carry scheme for field programmable gate arrays

A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.
Owner:MICROSEMI SOC

Tree shaped fast connection establishing method based on multi-Agent cooperation

ActiveCN101488898APrevent false reservationsPrevents errors from being preempted by other requestsStar/tree networksStructure of Management InformationConnection control
The invention relates to the communication field, the invention embodiment discloses a tree-shaped fast connecting establishing method based on multiple-Agent cooperation. The method comprises: an integral establishing process flow of single service tree-shaped signaling; a signaling expanding abstraction logical function in a network with control plane; a topological abstract method of multiple-Agent collaboration signaling forwarding tree; a traversing mode of tree-shaped signaling forwarding tree based on non-balance type binary forwarding tree; a traversing mode of tree-shaped signaling forwarding tree based on non-balance type N-branch forwarding tree; a resource invalidation processing method in the tree-shaped signaling service process flow. According to the method of the invention, the entity logical function can be forwarded by expanding the signaling, the connection control operation can be performed between a plurality of Agents to establish a layered structure for a calling connection controller, the higher grade calling connection controller implements the control function for a first stage calling connection controller to rapidly implement the connection establishment and respectively provide processing flows for different resource invalidation conditions. After considering the queue processing and exterior transmission time delay, the connection can be optimized by a non-standard binary forwarding tree structure. The tree-shaped signaling implementing interface of the multiple-Agent system comprises a GUI interface for taking charge of the transmitting of the control command, the real-time data detection, the data filtering, the center resource database access and the Agent information report and so on operations.
Owner:BEIJING UNIV OF POSTS & TELECOMM +1
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