44 results about "Clock shift" patented technology

A source driver of the liquid crystal display comprising: an (n / 3)-clock shift register for shifting a horizontal synchronous signal pulse, to output a latch clock; a first sampling latch for sampling and latching digital video signals corresponding to odd-numbered column lines among 2n column lines according to the latch clock sent from the shift register; a second sampling latch for sampling and latching digital video signals corresponding to even-numbered column lines among 2n column lines according to the latch clock outputted from the shift register; a holding latch for receiving and latching the data stored in the first sampling latch according to a first load signal, and for receiving and latching the data stored in the second sampling latch according to a second load signal; a D / A converter for converting the digital video signals corresponding to the odd-numbered column lines or the digital video signals corresponding to the even-numbered column lines, stored in the holding latch, into analog data signals; and an amplifier for amplifying the analog video signals corresponding to the odd-numbered column lines or the analog video signals corresponding to the even-numbered column lines, supplied from the D / A converter.

A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.

A communication system and a timing control method are proposed that optimize timing in a sender and thereby enable information to be stably transmitted at the right timing. Under instructions from a timing controller in a receiver, the timing of driving a phase modulator in a sender is shifted by one step after another, and the then amount of clock shift and result of interference are monitored at the receiver and stored in a memory. The optimum timing is determined based on the stored data. Thus, a clock for driving the phase modulator in the sender can be set at the right timing. This is equivalent to compensating for group velocity dispersion due to wavelength dispersion that occurs when an optical signal channel and a clock signal channel are transmitted by wavelength division multiplexing transmission.

Presented herein are system(s) and method(s) for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing. In one embodiment, there is presented a system for scan testing. The system comprises an ATE clock and a phase lock loop. The ATE clock shifts scan data. The phase lock loop generates capture pulses. The ATE clock or the capture pulses are selected based on an external synchronization signal.

An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block column address is provided. In particular, a data input apparatus improving a data processing speed by advancing an operation time point of a data bus writer is provided.

A communication system and a timing control method are proposed that optimize timing in a sender and thereby enable information to be stably transmitted at the right timing. Under instructions from a timing controller in a receiver, the timing of driving a phase modulator in a sender is shifted by one step after another, and the then amount of clock shift and result of interference are monitored at the receiver and stored in a memory. The optimum timing is determined based on the stored data. Thus, a clock for driving the phase modulator in the sender can be set at the right timing. This is equivalent to compensating for group velocity dispersion due to wavelength dispersion that occurs when an optical signal channel and a clock signal channel are transmitted by wavelength division multiplexing transmission.