32 results about "Branch trace" patented technology

In a method for testing computer code, each branch that occurs within the machine-readable code is located. A first tracepoint is placed immediately after the beginning of the branch and a second tracepoint at the target address of each branch, each tracepoint generating an indicator. When the machine-readable code with the tracepoints is executed on the target computer, the method identifies those indicators that have been generated by their corresponding tracepoints, thereby permitting determination of those branches that the program control flow has not passed through. The test cases are modified to exercise the previously omitted branches, and the converted code is re-executed, until all branches have been properly exercised. The tracepoints are automatically eliminated after they have performed their intended function.

A method includes stalling a call to a critical operating system (OS) function and determining whether branch trace records of the call include a return instruction. Upon a determination that the branch trace records of the call do include a return instruction, the method further includes taking protective action to protect a computer system.

A module board has trace impedances that are matched at trace junctions. An input line that drives a signal to a junction has its impedance adjusted to match the equivalent impedance of branch traces output from the junction. Since input and output impedances match, reflections caused by the junction are minimized or eliminated. The input impedance can match by being within 20% of the equivalent impedance of the branch lines. The equivalent impedance of branches is the reciprocal of the sum of the individual branch lines' reciprocal impedance. Termination can be eliminated when such junctions are impedance-matched. Secondary junctions can also be impedance-matched, allowing for a variety of trace topologies. Such trace-impedance matching is especially useful for memory modules.

Exemplary methods, apparatuses, and systems assign a plurality of branch instructions within a computer program to a plurality of prime numbers. Each branch instruction is assigned a unique prime number within the plurality of prime numbers. A run-time branch trace value is determined to be divisible, without a remainder, by a first prime number of the plurality of prime numbers. The run-time branch trace value was generated during execution of the computer program. An output is generated indicating that a first branch instruction assigned to the first prime number was executed.

Exemplary methods, apparatuses, and systems generate a plurality of possible branch traces for a computer program. Each possible branch trace represents different sequences of branch instructions that may be executed while the computer program is running. Each branch instruction has a corresponding identifier. A branch trace value is generated for at least one of the plurality of possible branch traces. Generating the branch trace value includes performing a mathematical or logical operation between a first identifier and each subsequent identifier of the possible branch trace to obtain the branch trace value. An output including a branch trace is generated based upon a match between a run-time branch trace value and the at least one generated branch trace value.

Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA) / microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA / microarchitecture set to obtain first execution results.

A linker generates a simulator-use executable format program from a pre-conversion object program and a simulator-use object program. A simulator executes the simulator-use object program and acquires branch trace information. A binary program converting tool, based on the branch trace information and a branch penalty table, generates a post-conversion object program having a rewritten branching prediction bit of the pre-conversion object program. Another linker generates an actual-machine-use executable format program from the post-conversion object program and an actual-machine-use object program.

The invention discloses a process for controlling particle size of nano calcium carbonate for sulfur fixation by an alternating magnetic field and relates to the technical field of technologies. The process comprises the steps: additionally arranging the alternating magnetic field outside a reactor; enabling a calcium hydroxide solution to flow through the alternating magnetic field at the rate of 12m / s to 15m / s, and meanwhile, enabling a branch trace solution to enter a microscope observation range from a main passage of the calcium hydroxide solution; slowly introducing CO2 gas into the calcium hydroxide solution, controlling the flow rate of introduced CO2 gas by a flowmeter, and observing the moment when microscopic crystals appear, i.e., appropriate CO2 gas flow; and maintaining the CO2 gas flow until crystallization is completed. According to the process for controlling the particle size of the nano calcium carbonate for sulfur fixation by the alternating magnetic field, disclosed by the invention, by the alternating magnetic field, the agglomeration among calcium carbonate grains is controlled, the dimensional stability is improved, and the phase interfacial tension is lowered, so that the sulfur fixation reaction performance of the nano calcium carbonate is improved, the nano calcium carbonate can have relatively good sulfur fixation capability under the condition of low use level, and thus the field of application of the nano calcium carbonate is widened.

A linker generates a simulator-use executable format program from a pre-conversion object program and a simulator-use object program. A simulator executes the simulator-use object program and acquires branch trace information. A binary program converting tool, based on the branch trace information and a branch penalty table, generates a post-conversion object program having a rewritten branching prediction bit of the pre-conversion object program. Another linker generates an actual-machine-use executable format program from the post-conversion object program and an actual-machine-use object program.

The invention relates to a novel broadband PCB antenna suitable for a Wireless Local Area Network (WLAN). The novel broadband PCB antenna includes a printed circuit board and an antenna radiation unit, the antenna radiation unit is located on the printed circuit board, the antenna radiation unit and the printed circuit board serve as antenna system, a grounding wire is located on an edge of the antenna radiation unit and the printed circuit board, a first radiating body is arranged beside the grounding wire, and a second radiating body, the grounding wire and a third radiating body form a broadband loop antenna; the third radiating body is coupled to a lower side metal floor plate; a fourth radiating body serves as a branch line of an antenna radiating body and is located at an included angle position of two side faces of the metal floor plate. Three principles of forming the loop antenna, antenna branch line and antenna ground coupling are utilized to realize broadband radiation impedance, thereby realizing antenna effective radiation in an ultra-wide range of 1.36GHz to 8GHz, covering a WLAN 2.4GHz frequency band and a 5GHz frequency band, and having very high robustness to surrounding environment of the antenna.

An embodiment of the present invention includes a method for analyzing and solving possibility tree. A possibility tree having a plurality of programmable nodes is constructed and solved with a solver module executed by a processor element. The solver module executes the programming of said nodes, and tracks the state of at least a variable through a branch. When a variable of said branch is out of tolerance with a parameter, the solver disables remaining nodes of the branch and marks the branch as an invalid solution. The valid solutions are then aggregated and displayed as valid tree solutions.

An analysis function imparting device according to the present invention includes processing circuitry configured to execute a script engine while monitoring the script engine to acquire an execution trace including an application programming interface (API) trace and a branch trace, analyze the execution trace, and detect a hook point that is a location to which a hook is applied and a code for analysis is inserted, detect, based on monitoring at the hook point, a tap point that is a memory monitoring location at which the code for analysis outputs a log, and apply a hook to the script engine to impart an analysis function to the script engine based on the hook point and the tap point.

A device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type, said device including: means for receiving a first signal representative of an actually executed instruction; means for receiving a second signal representative of an expanded instruction; means for receiving a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by said microcontroller, microprocessor or data processing unit; means for storing consecutive addresses pointed by a program counter; means for processing said first, second and third signals in order to determine a pair comprised of a source address and a destination address for an address branch, when appropriate; and means for storing said address pair.

The invention discloses a branch protection switching circuit, relating to a network equipment protection circuit. And the branch protection switching circuit comprises driving end, at least a working plate and at least a protection plate, where the working plate and the protection plate are equipped with switch and processing chip, respectively, the driving end is branched into at least two branches which are connected through the switch with the processing chip; and also comprises at least two impedance matching networks whose first ends are connected to the said branches, respectively and whose second ends are connected to power supply VCC or ground. And it can improve signal transmission quality of interconnected systems with longer branched traces, and implement reliable protection for the interconnected systems.

Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA) / microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA / microarchitecture set to obtain first execution results.

The present invention relates to a hardwave-based edge profiling method and system. The method comprising: counting each occurrence of a hardware event by a Performance Monitoring Counter of a hardware processor during the execution of a target program code; orderly and continuously storing in a buffer of a Taken Branch Trace (TBT) Facility of said hardware processor a predefined TBT size of last taken branches of said target program code during its execution; every time said counting equals a sampling rate, triggering sampling of said buffer, to receive a TBT comprising current said predefined TBT size of last taken branches; constructing a full branch trace for each said TBT based on said target program code; extracting a predefined Chopped Branch Trace (CBT) size of last branches from each said full branch trace, to receive a chopped branch trace for said each TBT; and incrementally storing each said chopped branch trace to generate an edge profile of said target program code.

A system and method tests computer software using tracking bits in branch instructions to track portions of the software that have been tested. The tracking bits are bits of a branch programming instruction and may be repurposed hint bits used in the prior art to control pre-fetch of instructions. A branch tracking unit sets bits in a branch instruction of an application or program being tested. The branch tracing unit sets a first bit if a branch is taken and sets a second tracking bit if the branch is not taken. The modified program instructions can be analyzed after running the test inputs to determine if any branches in the software have not been exercised by the test inputs.

A testing unit including a substrate, a plurality of vias located in the substrate, a plurality of pin traces having a height and a width and each extending from a respective via towards an edge of the substrate, a plurality of end traces having a height and a width with each end trace extending from an end of a respective pin trace towards the edge of the substrate, a plurality of branch traces having a height and a width and each extending from a side of a respective pin trace, a plurality of traces extending from the end of a respective end trace, branch trace or pin trace to the edge of the substrate, where each end trace is adjacent to a respective branch trace, each end trace is adjacent to a respective branch trace on one side and a pin trace on the opposite side, and each pin trace is adjacent to another pin trace on one side.

The disclosure relates to a testing apparatus for a high speed communications jack and methods of operating the same. A testing unit including a substrate, a plurality of vias located in the substrate, a plurality of pin traces having a height and a width and each extending from a respective via towards an edge of the substrate, a plurality of end traces having a height and a width with each end trace extending from an end of a respective pin trace towards the edge of the substrate, a plurality of branch traces having a height and a width and each extending from a side of a respective pin trace, a plurality of traces extending from the end of a respective end trace, branch trace or pin trace to the edge of the substrate, where each end trace is adjacent to a respective branch trace.