A data transfer
bus system is provided which is able to carry out effective
processing of interrupt. To an AHB (Advanced High performance
Bus) of an AMBA (Advanced Micro-controller
Bus Architecture)
system, connected are an AHB
bus interface connected to an ARM CPU, an AHB
bus arbiter, an AHB-APB bridge, a high-performance
peripheral device and a bus request priority determining circuit. Further, to the AHB-APB bridge, a
timer and a UART device, etc., are connected via the
peripheral bus (APB). The interrupt controller to which
interrupt request signals are inputted outputs an interrupt
signal to the ARM CPU and the bus request priority determining circuit, and decides whether to generate the bus request sent from the high-performance
peripheral device, according to the priority
ranking of the interrupt and the bus request.