A
converter circuit is specified for switching of a multiplicity of switching
voltage levels, which have n first switching groups (1.1, . . . , 1.n) for each phase (R, S, T), with the n-th first switching group (1.n) being formed by a first drivable bidirectional power
semiconductor switch (2) and a second drivable bidirectional power
semiconductor switch (3), and with the first first switching group (1.1) to the (n−1)-th switching group (1.(n−1)) each being formed by a first drivable bidirectional power
semiconductor switch (2) and a second drivable bidirectional power semiconductor switch (3), and by a
capacitor (4) which is connected to the first and second drivable bidirectional power semiconductor switches (2, 3) with each of the n first switching groups (1.1, . . . , 1.n) being connected in a linked form to the respectively adjacent first switching group (1.1, . . . , 1.n), and with the first and the second drivable bidirectional power semiconductor switches (2, 3) in the first first switching group (1.1) being connected to one another. In order to reduce the stored electrical energy in the
converter circuit, n≧1, and p second switching groups (5.1, . . . , 5.p) and p third switching groups (6.1, . . . , 6.p) are provided, which each have a first drivable bidirectional power semiconductor switch (7, 8), a second drivable bidirectional power semiconductor switch (9, 10) and a
capacitor (13, 14), where p≧1. Each of the p second switching groups (5.1, . . . , 5.p) is connected in a linked form to the respectively adjacent second switching group (5.1, . . . , 5.p), and each of the p third switching groups (6.1, . . . , 6.p) is connected in a linked form to the respectively adjacent third switching group (6.1, . . . , 6.p). Furthermore, the first second and the first third switching group (5.1, 6.1) each have a third drivable bidirectional power semiconductor switch (11, 12) which is connected back-to-back in series with the respective second drivable bidirectional power semiconductor switch (9, 10), with the first second switching group (5.1) being connected to the first drivable bidirectional power semiconductor switch (2) in the n-th first switching group (1.n), and with the first third switching group (6.1) being connected to the second drivable bidirectional power semiconductor switch (3) in the n-th first switching group (1.n), and the
capacitor (13) in the p-th second switching group (5.p) is connected in series with the capacitor (14) in the p-th third switching group (6.p).